CYDM064B16
CYDM128B16
CYDM256B16
1.8 V 4 K/8 K/16 K 16
MoBL Dual-Port Static RAM
1.8V 4K/8K/16K x 16 MoBL Dual-Port Static RAM
Features
True dual ported memory cells that allow simultaneous access Expandable data bus to 32-bits with Master or Slave chip select
of the same memory location when using more than one device
4, 8, or 16K 16 organization On-chip arbitration logic
Ultra Low operating power Semaphores included to permit software handshaking
between ports
Active: ICC = 15 mA (typical) at 55 ns
Standby: I = 2 A (typical)
SB3
Input read registers and output drive registers
Small footprint: available in a 6x6 mm 100-pin Pb-free vfBGA
INT flag for port-to-port communication
Port independent 1.8V, 2.5V, and 3.0V I/Os
Separate upper-byte and lower-byte control
Full asynchronous operation
Industrial temperature ranges
Automatic power down
Pin select for Master or Slave
Selection Guide for V = 1.8V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter Unit
(-55)
Port I/O Voltages (P1-P2) 1.8V -1.8V V
Maximum Access Time 55 ns
Typical Operating Current 15 mA
Typical Standby Current for I 2 A
SB1
Typical Standby Current for I 2 A
SB3
Selection Guide for V = 2.5V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter Unit
(-55)
Port I/O Voltages (P1-P2) 2.5V-2.5V V
Maximum Access Time 55 ns
Typical Operating Current 28 mA
Typical Standby Current for I 6 A
SB1
Typical Standby Current for I 4 A
SB3
Selection Guide for V = 3.0V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter Unit
(-55)
Port I/O Voltages (P1-P2) 3.0V-3.0V V
Maximum Access Time 55 ns
Typical Operating Current 42 mA
Typical Standby Current for I 7 A
SB1
Typical Standby Current for I 6 A
SB3
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-00217 Rev. *I Revised March 10, 2014 CYDM064B16
CYDM128B16
CYDM256B16
[1, 2]
Logic Block Diagram
IO[15:0]
R
IO[15:0]
L
UB
R
UB
L
LB
LB R
L
IO
IO
Control
Control
16K X 16
Dual Ported Array
Address Decode Address Decode
A[13:0]
L A [13:0]
R
CE
L CE
R
Interrupt
OE
L OE
R
Arbitration
R/W
R/W R
L
Semaphore
SEM
R
SEM
L
BUSY
R
BUSY
L
M/S
INT Mailboxes
L INT
R
Input Read
Register and
CE CE
L R
Output Drive
OE OE
L R
Register
R/W R/W
L R
IRR ,IRR
0 1
ODR - ODR
0 4
SFEN
Notes
1. A A for 4K devices; A A for 8K devices; A A for 16K devices.
0 11 0 12 0 13
2. BUSY is an output in master mode and an input in slave mode.
Document Number: 001-00217 Rev. *I Page 2 of 27