CYDM064B16 CYDM128B16 CYDM256B16 1.8 V, 4K/8K/16K 16 MoBL Dual-Port Static RAM 1.8 V, 4K/8K/16K 16 MoBL Dual-Port Static RAM Features Functional Description True dual ported memory cells that allow simultaneous access The CYDM256B16, CYDM128B16, and CYDM064B16 are low of the same memory location power CMOS 4K, 8K,16K 16 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when 4, 8, or 16K 16 organization multiple processors access the same piece of data. Two ports are provided that permit independent, asynchronous access for Ultra Low operating power reads and writes to any location in memory. The devices can be Active: ICC = 15 mA (typical) at 55 ns used as standalone 16-bit dual-port static RAMs or multiple Standby: I = 2 A (typical) SB3 devices can be combined to function as a 32-bit or wider Small footprint: available in a 6 6 mm 100-pin Pb-free vfBGA master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the Port independent 1.8 V, 2.5 V, and 3.0 V I/Os need for separate master and slave devices or additional discrete logic. Application areas include interprocessor or multi- Full asynchronous operation processor designs, communications status buffering, and Automatic power down dual-port video or graphics memory. Pin select for Master or Slave Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are Expandable data bus to 32-bits with Master or Slave chip select provided on each port (BUSY and INT). BUSY indicates that the when using more than one device port is trying to access the same location currently being On-chip arbitration logic accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems through a mail box. Semaphores included to permit software handshaking The semaphores are used to pass a flag or token, from one port between ports to the other, to indicate that a shared resource is in use. The Input read registers and output drive registers semaphore logic consists of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a INT flag for port-to-port communication semaphore indicates that a shared resource is in use. An Separate upper-byte and lower-byte control automatic power down feature is controlled independently on Industrial temperature ranges each port by a Chip Enable (CE) pin. The CYDM256B16, CYDM128B16, CYDM064B16 are available in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00217 Rev. *K Revised April 12, 2018 CYDM064B16 CYDM128B16 CYDM256B16 Selection Guide for V = 1.8V CC CYDM256B16/CYDM128B16/CYDM064B16 Parameter Unit (-55) Port I/O Voltages (P1P2) 1.8 V1.8 V V Maximum Access Time 55 ns Typical Operating Current 15 mA Typical Standby Current for I 2 A SB1 Typical Standby Current for I 2 A SB3 Selection Guide for V = 2.5 V CC CYDM256B16/CYDM128B16/CYDM064B16 Parameter Unit (-55) Port I/O Voltages (P1P2) 2.5 V2.5 V V Maximum Access Time 55 ns Typical Operating Current 28 mA Typical Standby Current for I 6 A SB1 Typical Standby Current for I 4 A SB3 Selection Guide for V = 3.0 V CC CYDM256B16/CYDM128B16/CYDM064B16 Parameter Unit (-55) Port I/O Voltages (P1P2) 3.0 V3.0 V V Maximum Access Time 55 ns Typical Operating Current 42 mA Typical Standby Current for I 7 A SB1 Typical Standby Current for I 6 A SB3 Document Number: 001-00217 Rev. *K Page 2 of 33