Data Sheet April 2012 DS3102 Stratum 2/3E/3 Timing Card IC with Synchronous Ethernet Support General Description Features Synchronization for Stratum 2, 3E, 3, 4E and 4 The DS3102 is a low-cost, feature-rich timing IC for plus SMC, SEC and EEC telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of Meets Requirements of GR-1244 Stratum 2 4, GR-253, G.812 Types I IV, G.813, and G.8262 line cards and external timing from external DS1/E1 Stratum 2, 3E or 3 Holdover Accuracy with BITS transceivers. The DS3102 continually monitors all Suitable External Oscillator input clocks and performs automatic hitless reference Programmable Bandwidth: 0.5mHz to 400Hz switching if the primary reference fails. The T0 DPLL Hitless Reference Switching on Loss of Input complies with the Stratum 2, 3E, 3, 4E and 4 Automatic or Manual Phase Build-Out requirements of GR-1244, GR-253, G.812 Types I IV, Frequency Conversion Among SONET/SDH, G.813 and G.8262. The highly programmable DS3102 PDH, Ethernet, Wireless, and CMTS Rates support numerous input and output frequencies including rates required for SONET/SDH, 8 Input Clocks Synchronous Ethernet (1G, 10G, and 100Mbps), Four CMOS/TTL Inputs ( 125MHz) wireless base stations, and CMTS systems. PLL Four LVDS/LVPECL/CMOS/TTL Inputs ( 156.25MHz) bandwidths from 0.5mHz to 400Hz are supported, Three Optional Frame-Sync Inputs (CMOS/TTL) and a wide variety of PLL characteristics and device Continuous Input Clock Quality Monitoring features can be configured to meet the needs of Numerous Input Clock Frequencies Supported: many different applications. Two DS3102 devices can SONET/SDH: 6.48, N x 19.44, N x 51.84MHz be configured in a master/slave arrangement for timing Ethernet xMII: 2.5, 25, 125, 156.25MHz card equipment protection. PDH: N x DS1, N x E1, N x DS2, DS3, E3 Frame Sync: 2kHz, 4kHz, 8kHz The DS3102 register set is backward compatible with Custom: Any Multiple of 2kHz Up to 131.072MHz, Semtechs ACS8522 timing card IC. The DS3102 has a Any Multiple of 8kHz Up to 155.52MHz different package and pin arrangement than the 7 Output Clocks ACS8522. Three CMOS/TTL Outputs ( 125MHz) Two LVDS/LVPECL Outputs ( 312.50MHz) Applications Two Dual CMOS/TTL and LVDS/LVPECL Outputs SONET/SDH Equipment Clocks (SECs) Five CMOS Outputs Have Additional Output Pins Synchronous Ethernet Equipment Clocks (EECs) That Can Be Powered at 2.5V or 3.3V Timing Card IC in WAN Equipment Including MSPPs, Numerous Output Clock Frequencies Supported: Ethernet Switches, Routers, DSLAMs, and SONET/SDH: 6.48, N x 19.44, N x 51.84MHz Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz Wireless Base Stations PDH: N x DS1, N x E1, N x DS2, DS3, E3 Other: 10, 10.24, 13, 30.72MHz Ordering Information Frame Sync: 2kHz, 8kHz Custom Clock Rates: Any Multiple of 2kHz Up to PART TEMP RANGE PIN-PACKAGE 77.76MHz, Any Multiple of 8kHz Up to 2 DS3102GN -40 C to +85 C 81 CSBGA (10mm) 311.04MHz, Any Multiple of 10kHz Up to 2 DS3102GN+ -40 C to +85 C 81 CSBGA (10mm) 388.79MHz General +Denotes a lead(Pb)-free/RoHS-compliant package. Internal Compensation for Master Clock Oscillator SPI Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) Industrial Temperature Range 1 DS3102 Table of Contents 1. STANDARDS COMPLIANCE ....................................................................................................... 6 2. APPLICATION EXAMPLE ............................................................................................................ 7 3. BLOCK DIAGRAM ........................................................................................................................ 8 4. DETAILED DESCRIPTION ............................................................................................................ 9 5. DETAILED FEATURES ............................................................................................................... 11 5.1 INPUT CLOCK FEATURES ............................................................................................................ 11 5.2 T0 DPLL FEATURES ................................................................................................................... 11 5.3 T4 DPLL FEATURES ................................................................................................................... 11 5.4 OUTPUT APLL FEATURES ........................................................................................................... 12 5.5 OUTPUT CLOCK FEATURES ......................................................................................................... 12 5.6 REDUNDANCY FEATURES ............................................................................................................ 12 5.7 GENERAL FEATURES .................................................................................................................. 12 6. PIN DESCRIPTIONS ................................................................................................................... 13 7. FUNCTIONAL DESCRIPTION .................................................................................................... 17 7.1 OVERVIEW ................................................................................................................................. 17 7.2 DEVICE IDENTIFICATION AND PROTECTION ................................................................................... 18 7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ........................................................... 18 7.4 INPUT CLOCK CONFIGURATION .................................................................................................... 19 7.4.1 Signal Format Configuration ................................................................................................................ 19 7.4.2 Frequency Configuration ...................................................................................................................... 20 7.5 INPUT CLOCK MONITORING ......................................................................................................... 21 7.5.1 Frequency Monitoring .......................................................................................................................... 21 7.5.2 Activity Monitoring ................................................................................................................................ 21 7.5.3 Selected Reference Activity Monitoring ............................................................................................... 22 7.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING .................................................................. 23 7.6.1 Priority Configuration ............................................................................................................................ 23 7.6.2 Automatic Selection Algorithm ............................................................................................................. 23 7.6.3 Forced Selection .................................................................................................................................. 24 7.6.4 Ultra-Fast Reference Switching ........................................................................................................... 24 7.6.5 External Reference Switching Mode .................................................................................................... 24 7.6.6 Output Clock Phase Continuity During Reference Switching .............................................................. 25 7.6.7 Frequency Monitoring Hysteresis Required by Telcordia GR-1244-CORE ......................................... 25 7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 26 7.7.1 T0 DPLL State Machine ....................................................................................................................... 27 7.7.2 T4 DPLL State Machine ....................................................................................................................... 30 7.7.3 Bandwidth ............................................................................................................................................ 32 7.7.4 Damping Factor .................................................................................................................................... 32 7.7.5 Phase Detectors ................................................................................................................................... 32 7.7.6 Loss-of-Lock Detection ........................................................................................................................ 33 7.7.7 Phase Build-Out ................................................................................................................................... 34 7.7.8 Input to Output (Manual) Phase Adjustment ........................................................................................ 35 7.7.9 Phase Recalibration ............................................................................................................................. 35 7.7.10 Frequency and Phase Measurement ................................................................................................... 35 7.7.11 Input Jitter and Wander Tolerance ....................................................................................................... 37 7.7.12 Jitter and Wander Transfer .................................................................................................................. 37 7.7.13 Output Jitter and Wander ..................................................................................................................... 38 7.8 OUTPUT CLOCK CONFIGURATION ................................................................................................ 38 7.8.1 Signal Format Configuration ................................................................................................................ 39 7.8.2 Frequency Configuration ...................................................................................................................... 39 2