Data Sheet April 2012 DS3104-SE Line Card Timing IC with Synchronous Ethernet Support Features General Description Timing Card to Line Card Path The DS3104-SE is a low-cost, feature-rich timing IC for Two Input Clocks from Master and Slave Timing line cards with Synchronous Gigabit Ethernet (GbE), Cards (LVDS/LVPECL or CMOS/TTL) 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. Optional Frame-Sync Inputs and Outputs ITU-T recommendation G.8261 (formerly G.pactiming) Continuous Input Clock Quality Monitoring specifies that network synchronization can be carried Hitless Reference Switching, Automatic or Manual over packet links by synchronizing the bit clock of the Holdover on Loss of All Inputs physical layer as is currently done on SONET/SDH Programmable PLL Bandwidth, 0.1Hz to 400Hz links. The DS3104-SE enables synchronization in Frequency Conversion Between SONET/SDH Ethernet line cards in both the transmit and receive Rates and Ethernet MII/GMII/XGMII Rates directions. Up to 7 Output Clocks: 3 CMOS/TTL ( 125MHz), 2 LVDS/LVPECL ( 312.50MHz), and 2 Dual In the transmit direction, the device accepts traditional CMOS/TTL and LVDS/LVPECL SONET/SDH system clocks such as 19.44MHz from Line Card to Timing Card Path redundant system timing cards and synthesizes Up to 8 Input Clocks: 4 CMOS/TTL ( 125MHz) frequency-locked xMII clock rates, such as the 125MHz and 4 LVDS/LVPECL/CMOS/TTL ( 156.25MHz) GTX CLK for GbE GMIIs. Each Ethernet PHY then Hitless Reference Switching, Automatic or Manual synthesizes a transmit bit clock that is frequency-locked Frequency Conversion Between Ethernet to the xMII clock, and thus to the system clock and MII/GMII/XGMII and SONET/SDH Rates network clock. In the receive direction, each PHY Two Output Clocks to Master and Slave Timing divides down the recovered bit clock to produce the Cards (CMOS/TTL or LVDS/LVPECL) receive xMII clock. The DS3104-SE accepts the xMII clock from any of several Ethernet ports and forwards a General frequency-locked system clock, such as 19.44MHz, to Suitable Line Card IC for Stratum 3/3E/4, SMC, the system timing cards. SONET/SDH ports are also SEC supported. Numerous Input Clock Frequencies Supported Ethernet xMII: 2.5, 25, 125, 156.25MHz Applications SONET/SDH: 6.48, N x 19.44, N x 51.84MHz PDH: N x DS1, N x E1, N x DS2, DS3, E3 Line Cards with Any Mix of Synchronous Ethernet and Frame Sync: 2kHz, 4kHz, 8kHz SONET/SDH Ports in WAN Equipment Including Custom: Any Multiple of 2kHz Up to 131.072MHz, MSPPs, Ethernet Switches, Routers, DSLAMs, and Any Multiple of 8kHz Up to 155.52MHz Wireless Base Stations Numerous Output Clock Frequencies Ordering Information Supported Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz PART TEMP RANGE PIN-PACKAGE SONET/SDH: 6.48, N x 19.44, N x 51.84MHz 2 DS3104GN -40 C to +85 C 81 CSBGA (10mm) PDH: N x DS1, N x E1, N x DS2, DS3, E3 2 Other: 10, 10.24, 13, 30.72MHz DS3104GN+ -40 C to +85 C 81 CSBGA (10mm) Frame Sync: 2kHz, 8kHz +Denotes a lead(Pb)-free/RoHS-compliant package. Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to SPI is a trademark of Motorola, Inc. 388.79MHz Internal Compensation for Master Clock Oscillator SPI Processor Interface 1.8V Operation with 2.5V/3.3V I/O (5V Tolerant) 1 DS3104-SE Table of Contents 1. STANDARDS COMPLIANCE ....................................................................................................... 6 2. APPLICATION EXAMPLE ............................................................................................................ 7 3. BLOCK DIAGRAM ........................................................................................................................ 8 4. DETAILED DESCRIPTION ............................................................................................................ 9 5. DETAILED FEATURES ............................................................................................................... 11 5.1 INPUT CLOCK FEATURES ............................................................................................................ 11 5.2 TIMING CARD TO LINE CARD DPLL FEATURES (T0 DPLL) ............................................................ 11 5.3 LINE CARD TO TIMING CARD DPLL FEATURES (T4 DPLL) ............................................................ 11 5.4 OUTPUT APLL FEATURES ........................................................................................................... 12 5.5 OUTPUT CLOCK FEATURES ......................................................................................................... 12 5.6 GENERAL FEATURES .................................................................................................................. 12 6. PIN DESCRIPTIONS ................................................................................................................... 13 7. FUNCTIONAL DESCRIPTION .................................................................................................... 17 7.1 OVERVIEW ................................................................................................................................. 17 7.2 DEVICE IDENTIFICATION AND PROTECTION ................................................................................... 18 7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ........................................................... 18 7.4 INPUT CLOCK CONFIGURATION .................................................................................................... 19 7.4.1 Signal Format Configuration ................................................................................................................ 19 7.4.2 Frequency Configuration ...................................................................................................................... 20 7.5 INPUT CLOCK MONITORING ......................................................................................................... 21 7.5.1 Frequency Monitoring .......................................................................................................................... 21 7.5.2 Activity Monitoring ................................................................................................................................ 21 7.5.3 Selected Reference Activity Monitoring ............................................................................................... 21 7.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING .................................................................. 22 7.6.1 Priority Configuration ............................................................................................................................ 22 7.6.2 Automatic Selection Algorithm ............................................................................................................. 22 7.6.3 Forced Selection .................................................................................................................................. 23 7.6.4 Ultra-Fast Reference Switching ........................................................................................................... 23 7.6.5 External Reference Switching Mode .................................................................................................... 24 7.6.6 Output Clock Phase Continuity During Reference Switching .............................................................. 24 7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 25 7.7.1 T0 DPLL State Machine ....................................................................................................................... 26 7.7.2 T4 DPLL State Machine ....................................................................................................................... 29 7.7.3 Bandwidth ............................................................................................................................................ 31 7.7.4 Damping Factor .................................................................................................................................... 31 7.7.5 Phase Detectors ................................................................................................................................... 31 7.7.6 Loss-of-Lock Detection ........................................................................................................................ 32 7.7.7 Phase Build-Out ................................................................................................................................... 33 7.7.8 Input to Output (Manual) Phase Adjustment ........................................................................................ 33 7.7.9 Phase Recalibration ............................................................................................................................. 33 7.7.10 Frequency and Phase Measurement ................................................................................................... 34 7.7.11 Input Jitter Tolerance ........................................................................................................................... 35 7.7.12 Jitter and Wander Transfer .................................................................................................................. 35 7.7.13 Output Jitter and Wander ..................................................................................................................... 36 7.8 OUTPUT CLOCK CONFIGURATION ................................................................................................ 37 7.8.1 Signal Format Configuration ................................................................................................................ 37 7.8.2 Frequency Configuration ...................................................................................................................... 37 7.9 FRAME AND MULTIFRAME ALIGNMENT .......................................................................................... 45 2