8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet The SST49LF008A flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of PC-BIOS applications. Features Firmware Hub for Intel 8xx Chipsets Two Operational Modes Firmware Hub Interface (FWH) Mode for 8 Mbit SuperFlash memory array for code/data In-System operation storage Parallel Programming (PP) Mode for fast production programming 1024K x8 Firmware Hub Hardware Interface Mode Flexible Erase Capability 5-signal communication interface supporting byte Read Uniform 4 KByte Sectors and Write Uniform 64 KByte overlay blocks 33 MHz clock frequency operation 64 KByte Top Boot Block protection WP and TBL pins provide hardware write Chip-Erase for PP Mode Only protect for entire chip and/or top Boot Block Block Locking Register for all blocks Single 3.0-3.6V Read and Write Operations Standard SDP Command Set Data Polling and Toggle Bit for End-of-Writedetection Superior Reliability 5 GPI pins for system design flexibility Endurance:100,000 Cycles (typical) 4 ID pins for multi-chip selection Greater than 100 years Data Retention Parallel Programming (PP) Mode Low Power Consumption 11-pin multiplexed address and Active Read Current: 6 mA (typical) 8-pin data I/O interface Standby Current: 10 A (typical) Supports fast In-System or PROM programming for manufacturing Fast Sector-Erase/Byte-Program Operation CMOS and PCI I/O Compatibility Sector-Erase Time: 18 ms (typical) Block-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) Packages Available Byte-Program Time: 14 s (typical) 32-lead PLCC Chip Rewrite Time: 15 seconds (typical) 32-lead TSOP (8mm x 14mm) Single-pulse Program or Erase 40-leadTSOP (10mm x 20mm) Internal timing generation Non-Pb (lead-free) packages available All non-Pb (lead-free) devicesareRoHScompliant 2011 Silicon Storage Technology, Inc. www.microchip.com DS25085A 10/118 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Product Description The SST49LF008A flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general pur- pose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of PC-BIOS applications. The SST49LF008A flash memory devices are manufactured with SSTs proprietary, high performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reli- ability and manufacturability compared with alternate approaches. The SST49LF008A devices signifi- cantly improve performance and reliability, while lowering power consumption. The SST49LF008A devices write (Program or Erase) with a single 3.0-3.6V power supply. They use less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any given volt- age range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF008A products provide a maximum Byte-Program time of 20 sec. The entire memory can be erased and programmed byte-by-byte typically in 15 seconds when using status detection features such as Toggle Bit or Data Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles performed. Therefore the system software or hardware does not have to be cal- ibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alterna- tive flash memory technologies, whose Erase and Program time increase with accumulated Erase/ Program cycles. To protect against inadvertent write, the SST49LF008A devices employ hardware and software data (SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead TSOP package. In addition, the SST49LF008A is offered in 32-lead PLCC and 40-lead TSOP pack- ages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions. 2011 Silicon Storage Technology, Inc. DS25085A 10/11 2