Precision Edge 3.3V, 3.2Gbps DIFFERENTIAL SY89545L Micrel, Inc. Precision Edge 4:1 LVDS MULTIPLEXER with SY89545L INTERNAL INPUT TERMINATION FEATURES Selects among four differential inputs Precision Edge Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput DESCRIPTION < 600ps In-to-Out t pd The SY89545L is a fast, low jitter 4:1 differential MUX < 150ps t /t r f with an LVDS (350mV) compatible output with guaranteed Ultra-low jitter design: data rate throughput of 3.2Gbps over temperature and < 1ps random jitter RMS voltage. < 10ps deterministic jitter PP The SY89545L differential inputs include a unique, 3-pin < 10ps total jitter (clock) internal termination that allows access to the termination PP network through a V pin. This feature allows the device to < 0.7ps crosstalk-induced jitter T RMS easily interface to different logic standards, both AC- and Unique input isolation design minimizes crosstalk DC-coupled without external resistor-bias and termination Internal input termination networks. The result is a clean, stub-free, low jitter interface Unique input termination and V pin accepts DC- solution. T coupled and AC-coupled inputs (LVDS, LVPECL, The SY89545L operates from a single 3.3V supply, and CML) is guaranteed over the full industrial temperature range 350mV LVDS output swing (40C to +85C). For applications that require a 2.5V supply, consider the SY89544U. For applications that require two CMOS/TTL compatible MUX select differential outputs, consider the SY89546U or Power supply 3.3V +10% SY89545L.The SY89545L is part of a Micrels Precision 40C to +85C temperature range Edge product family. All support documentation can be Available in 32-pin (5mm x 5mm) MLF package found on Micrels web site at www.micrel.com. APPLICATIONS FUNCTIONAL BLOCK DIAGRAM IN0 SONET/SDH channel select applications 50 Fiber Channel multi-channel select applications V T0 50 Gigabit Ethernet multi-channel select /IN0 4:1 MUX 0 TYPICAL PERFORMANCE IN1 50 V T1 LVDS 50 Output Amplitude /IN1 1 vs. Frequency Q 400 MUX /Q 350 IN2 2 300 50 V T2 250 50 S1 200 /IN2 S0 3 150 100 IN3 50 50 V T3 0 0123456 50 FREQUENCY (GHz) /IN3 SEL0 Precision Edge is a registered trademark of Micrel, Inc. SEL1 MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-060308 11 Issue Date: June 2008 hbwhelp micrel.com or (408) 955-1690 OUTPUT AMPLITUDE (mV) Precision Edge Micrel, Inc. SY89545L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 VCC VCC 23 /IN0 2 IN3 SY89545LMI MLF-32 Industrial SY89545L Sn-Pb VT0 3 22 VT3 (2) SY89545LMITR MLF-32 Industrial SY89545L Sn-Pb 4 21 IN0 /IN3 20 VCC 5 (3) VCC SY89545LMG MLF-32 Industrial SY89545L with Pb-Free SEL0 6 19 SEL1 Pb-Free bar-line indicator NiPdAu 7 18 GND GND (2, 3) VCC 8 17 VCC SY89545LMGTR MLF-32 Industrial SY89545L with Pb-Free 910 11 1213141516 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF 3. Recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 4, 2, 32, IN0, /IN0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 30, 27, 25, 23, 21 IN1, /IN1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally IN2, /IN2, terminates to a V pin through 50 . Note that these inputs will default to an indeterminate T IN3, /IN3 state if left open. Unused differential input pairs can be terminated by connecting one input to V and the complementary input to GND through a 1k resistor. The V pin is to be CC T left open in this configuration. Please refer to the Input Interface Applications section for more details. 3, 31, 26, 22 VT0, VT1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a V T VT2, VT3 pin. The V , V , V , V pins provide a center-tap to a termination network for T0 T1 T2 T3 maximum interface flexibility. See Input Interface Applications section for more details. 6, 19 SEL0, SEL1 These single-ended TTL/CMOS compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. 1, 5, 8, VCC Positive Power Supply: Bypass with 0.1 F0.01 F low ESR capacitors. The 0.01 F 17, 20, 24, 28, 29 capacitor should be as close to V pin as possible. CC 10, 11 Q, /Q Differential Outputs: This LVDS output pair is the output of the device. It is a logic function of the IN0, IN1, IN0, IN1 and SEL0 inputs. Please refer to the Truth Table for details. 7, 9, 12, 13, 16, 18 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed pad 14, 15 NC No connect. (Unused pins). M9999-060308 2 hbwhelp micrel.com or (408) 955-1690 IN1 GND Q VT1 /Q /IN1 GND VCC GND VCC NC IN2 NC VT2 GND /IN2