ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet April 2010 Features Synchronizes to clock-and-sync-pair to maintain Ordering Information minimal phase skew between inputs and outputs ZL30106QDG1 64 pin TQFP* Trays, Bake & Drypack Supports output wander and jitter generation *Pb Free Matte Tin specifications for SONET/SDH and PDH interfaces -40C to +85C Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, Provides lock, holdover and accurate reference 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz fail indication inputs Selectable loop filter bandwidth of 29 Hz or Provides a range of clock outputs: 922 Hz - 2.048 MHz (E1), 16.384 MHz and either Less than 24 ps intrinsic jitter on the 4.096 MHz and 8.192 MHz or 32.768 MHz and rms 19.44 MHz output clock, compliant with GR-253- 65.536 MHz CORE OC-3 and G.813 STM-1 specifications - 19.44 MHz (SONET/SDH) Less than 0.6 ns intrinsic jitter on all PDH output pp clocks and frame pulses - 1.544 MHz (DS1) and 3.088 MHz Selectable external master clock source: clock - a choice of 6.312 MHz (DS2), 8.448 MHz (E2), oscillator or crystal 44.736 MHz (DS3) or 34.368 MHz (E3) Simple hardware control interface Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Applications Provides automatic entry into Holdover and return Line card synchronization for SONET/SDH and from Holdover PDH systems Manual and automatic hitless reference switching Wireless base-station Network Interface Card between any combination of valid input reference AdvancedTCA and H.110 line cards frequencies BW SEL LOCK OUT SEL2 OSCi OSCo TIE CLR Master Clock C2o REF0 REF SYNC0 C4/C65o Virtual TIE Reference REF1 C8/C32o MUX Corrector REF SYNC1 C16o Circuit E1 DPLL REF2 Synthesizer F4/F65o F8/F32o REF FAIL0 F16o REF FAIL1 TIE Reference C1.5o DS1 Corrector Monitor REF FAIL2 Synthesizer Enable C3o APP SEL1:0 C19o SDH Synthesizer F2ko Mode Control C6/8.4/34/44o Programmable REF SEL1:0 Synthesizer OUT SEL1:0 State Machine Frequency RST Select MUX IEEE TRST 1149.1a MODE SEL1:0 HMS HOLDOVER TCK TDI TMS TDO Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved.ZL30106 Data Sheet Description The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs. The ZL30106 output clocks wander and jitter generation are compliant with the associated transport medium specifications. 2 Zarlink Semiconductor Inc.