Register Map: Section 6.2 ZL30169 Tiny 3-Input, 3-Output Clock Translator for OTN Data Sheet January 2018 Ordering Information Features ZL30169LDG1 32 Pin QFN Trays Input Clocks ZL30169LDF1 32 Pin QFN Tape and Reel Three inputs, two differential/CMOS, one CMOS Matte Tin Any input frequency from 1kHz to 1250MHz Package size: 5 x 5 mm (1kHz to 300MHz for CMOS) -40 C to +85 C Inputs continually monitored for activity and frequency accuracy Automatic or manual reference switching In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz) Low-Bandwidth DPLL Per-output supply pin with CMOS output Programmable bandwidth, 14Hz to 500Hz voltages from 1.5V to 3.3V Attenuates jitter up to several UI Precise output alignment circuitry and per- Freerun or holdover on loss of all inputs output phase adjustment Per-output enable/disable and glitchless Hitless reference switching start/stop (stop high or low) High-resolution holdover averaging General Features Digitally controlled phase adjustment Automatic self-configuration at power-up from Low-Jitter Fractional-N APLL and 3 Outputs internal EEPROM up to four configurations Any output frequency from <1Hz to 1035MHz pin-selectable High-resolution fractional frequency conversion Numerically controlled oscillator mode with 0ppm error Zero-delay mode with external feedback Easy-to-configure, encapsulated design 2 SPI or I C processor Interface requires no external VCXO or loop filter Easy-to-use evaluation software components Each output has independent dividers Applications Output jitter is typically 0.16 to 0.28ps RMS Telecom OTN and FEC frequency conversion (12kHz-20MHz integration band) Frequency conversion and jitter attenuation in a Outputs are CML or 2xCMOS, can interface to wide variety of equipment types LVDS, LVPECL, HSTL, SSTL and HCSL IC1P, IC1N OC1P, OC1N HSDIV1 HSDIV1 DIV1 Input Block DPLL APLL VDDO1 Hitless Switching, Divider, ~3.7 to 4.2GHz, IC2P, IC2N OC2P, OC2N Jitter Filtering, HSDIV2 Monitor, DIV2 Fractional-N Holdover VDDO2 Selector IC3P/GPIO3 OC3P, OC3N Figu re 8 Figure 9 Figure 10 HSDIV3 HSDIV2 DIV3 VDDO3 Microprocessor Port (SPI or I2C Serial) XA xtal and HW Control and Status Pins driver XB 2 Figure 1 - Functional Block Diagram 1 Microsemi Confidential Copyright 2018. Microsemi Corporation. All Rights Reserved. RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI ZL30169 Data Sheet Table of Contents 1. APPLICATION EXAMPLES .......................................................................................................... 5 2. DETAILED FEATURES ................................................................................................................. 5 2.1 INPUT BLOCK FEATURES ............................................................................................................... 5 2.2 DPLL FEATURES .......................................................................................................................... 5 2.3 APLL FEATURES .......................................................................................................................... 5 2.4 OUTPUT CLOCK FEATURES ........................................................................................................... 5 2.5 GENERAL FEATURES .................................................................................................................... 6 2.6 EVALUATION SOFTWARE ............................................................................................................... 6 3. PIN DIAGRAM ............................................................................................................................... 7 4. PIN DESCRIPTIONS ..................................................................................................................... 8 5. FUNCTIONAL DESCRIPTION .................................................................................................... 10 5.1 DEVICE IDENTIFICATION .............................................................................................................. 10 5.2 TOP-LEVEL CONFIGURATION ....................................................................................................... 10 5.2.1 APLL-Only Mode .................................................................................................................................. 10 5.2.2 DPLL+APLL Mode ............................................................................................................................... 11 5.2.3 Evaluation Software for Device Configuration ..................................................................................... 12 5.3 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ........................................................... 12 5.4 LOCAL OSCILLATOR OR CRYSTAL ................................................................................................ 12 5.4.1 External Oscillator ................................................................................................................................ 13 5.4.2 External Crystal and On-Chip Driver Circuit ........................................................................................ 13 5.4.3 Clock Doubler ....................................................................................................................................... 14 5.4.4 Ring Oscillator (for System Start-Up) ................................................................................................... 14 5.5 INPUT SIGNAL FORMAT CONFIGURATION ...................................................................................... 15 5.6 INPUT BLOCK: INPUT DIVIDER, MONITOR AND SELECTOR .............................................................. 15 5.6.1 Input Clock Inversion and High-Speed Dividers .................................................................................. 15 5.6.2 Input Clock Monitoring ......................................................................................................................... 16 5.6.2.1 External Monitoring ....................................................................................................................... 16 5.6.2.2 Monitor Priority and Validation Timer............................................................................................ 17 5.6.2.3 Input Monitor Configuration .......................................................................................................... 17 5.6.3 Input Clock Priority, Selection and Switching for the DPLL ................................................................. 17 5.6.3.1 Priority Configuration .................................................................................................................... 17 5.6.3.2 Automatic Selection ...................................................................................................................... 17 5.6.3.3 Manual Selection .......................................................................................................................... 18 5.6.3.4 External Reference Switching Mode............................................................................................. 18 5.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 18 5.7.1 DPLL Configuration .............................................................................................................................. 19 5.7.2 DPLL States ......................................................................................................................................... 19 5.7.3 DPLL Capabilities ................................................................................................................................. 19 5.7.4 Input Wander and Jitter Tolerance ....................................................................................................... 20 5.7.5 Jitter and Wander Transfer .................................................................................................................. 21 5.7.6 Output Jitter and Wander ..................................................................................................................... 21 5.7.7 Numerically Controlled Oscillator (NCO) Mode ................................................................................... 21 5.8 APLL CONFIGURATION ............................................................................................................... 22 5.8.1 APLL Input Selection and Frequency .................................................................................................. 22 5.8.1.1 APLL-Only Mode........................................................................................................................... 22 5.8.1.2 DPLL+APLL Mode ........................................................................................................................ 22 5.8.2 APLL Output Frequency....................................................................................................................... 22 5.8.3 APLL Phase Adjustment ...................................................................................................................... 23 2 Microsemi Confidential