ZL30244, ZL30245 Dual-Channel Any-to-Any Clock Multiplier and Frequency Synthesizer ICs Product Brief September 2015 Ordering Information Features ZL30244 LFG7 64 Pin LGA Trays Two Independent APLL Channels ZL30244 LFF7 64 Pin LGA Tape and Reel Four Input Clocks Per Channel ZL30245 LFG7 64 Pin LGA Trays ZL30245 LFF7 64 Pin LGA Tape and Reel One crystal/CMOS input Ni Au Two differential/CMOS inputs Package size: 5 x 10 mm One single-ended/CMOS input Any input frequency from 9.72MHz to 1250MHz -40 C to +85 C (9.72MHz to 300MHz for CMOS) Precise output alignment circuitry and per- Clock selection by pin or register control output phase adjustment Low-Jitter Fractional-N APLL and 3 Outputs Per Per-output enable/disable and glitchless Channel start/stop (stop high or low) Any output frequency from <1Hz to 1035MHz General Features High-resolution fractional frequency conversion Automatic self-configuration at power-up from with 0ppm error external (ZL30244) or internal (ZL30245) Easy-to-configure, encapsulated design EEPROM up to four configs, pin-selectable requires no external VCXO or loop filter 2 SPI or I C processor Interface components Numerically controlled oscillator mode Each output has independent dividers Spread-spectrum modulation mode Output jitter as low as 0.16ps RMS (12kHz- Space-saving 5x10mm LGA package 20MHz integration band) Easy-to-use evaluation software Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL Applications In 2xCMOS mode, the P and N pins can be Frequency conversion and frequency synthesis in different frequencies (e.g. 125MHz and 25MHz) a wide variety of equipment types Per-output supply pin with CMOS output voltages from 1.5V to 3.3V Each Channel: IC1P, IC1N OC1P, OC1N HSDIV1 HSDIV1 DIV1 APLL VDDO1 IC2P, IC2N HSDIV2 ~3.7 to 4.2GHz, OC2P, OC2N DIV2 Fractional-N NCO IC3P/GPIO3 VDDO2 HSDIV3 SS OC3P, OC3N HSDIV2 DIV3 XA xtal VDDO3 driver XB 2 Microprocessor Port (SPI or I2C Serial) and HW Control and Status Pins Channel A pins have these names plus A suffix. Channel B pins have these names plus B suffix. Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2015. Microsemi Corporation. All Rights Reserved. RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI ZL30244, ZL30245 Product Brief 1. Application Examples 122.88MHz or 153.6MHz 30.72MHz Channel A 122.88MHz or 153.6MHz 122.88MHz or 153.6MHz 2x 156.25MHz differential Channel B 125MHz CMOS 25MHz CMOS Figure 2 Base Station Clock Multiplication and Ethernet Frequency Synthesis 100MHz 50MHz Channel A 100MHz 100MHz mclk 125MHz differential CChhaannnneell BB Processor SPI 25MHz CMOS freq ctrl ((NNCCOO mmooddee)) 1PPS Figure 3 - PCI Express Clock Synthesis and NCO for IEEE1588 Slave Clock 2. Detailed Features 2.1 Input Clock Features Four input clocks per channel: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS Input clocks can be any frequency from 9.72MHz up to 1250MHz (differential) or 300MHz (CMOS) 2.2 APLL Features APLL with very high-resolution fractional (i.e. non-integer) multiplication per channel Any-to-any frequency conversion with 0ppm error Two high-speed dividers per channel (integers 4 to 15, half divides 4.5 to 7.5) Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter components Bypass mode supports system testing 2.3 Output Clock Features Three low-jitter output clocks per channel Each output can be one differential output or two CMOS outputs Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs) Output jitter as low as 0.16ps RMS (12kHz to 20MHz integration band) In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin (example: OC3P 125MHz, OC3N 25MHz) Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components Can produce PCIe clocks (PCIe gen. 1, 2 and 3) Sophisticated output-to-output phase alignment (among outputs in the same channel) Per-output phase adjustment with high resolution and unlimited range Per-output enable/disable Per-output glitchless start/stop (stop high or low) 2.4 General Features 2 SPI or I C serial microprocessor interface per channel 2 Microsemi Corporation