ZL81000 Dual BITS Transceiver and CC Receiver Data Sheet August 2018 General Description Ordering Information ZL81000 provides two DS1/E1/2048kHz transceivers (transmitters plus receivers) specifically designed for ZL81000GGG2 256 Pin CSBGA Trays BITS/SSU timing in carrier-class telecommunications equipment. Each transceiver provides full support for DS1, E1 and G.703 2048kHz synchronization signals Package size: 17 x 17 mm in and out and includes SSM message insertion and -40 C to +85 C extraction. The device also includes two composite clock (CC) receivers and two general-purpose CMOS clock inputs to provide additional support as needed Two Composite Clock Receivers for legacy interfaces. Compliant with Telcordia GR-378 composite clock, G.703 centralized clock, and G.703 Features Appendix II.1) Japanese sync interfaces Two Independent Multi-Protocol BITS/SSU Configurable for 50% or 5/8 duty cycle, 1V or Transmitters and Receivers 3V pulse amplitude, and 110 /120/133 Receive and transmit DS1, E1, 2048 kHz, and termination 6312 kHz timing signals Monitored for LOS, AMI violations, presence or Insert and extract SSM messages (DS1, E1) absence of 8 kHz component, and optionally DS1 SF or ESF formats the Japanese 400 Hz component E1 FAS, CAS and/or CRC-4 framing Followed by DPLL+APLL for jitter filtering and optional frequency conversion J1 support (DS1 with Japanese CRC-6 & RAI) Two programmable-frequency inputs Short-haul and long-haul line interfaces Operates from a single 12.8MHz local oscillator Internal software-selectable termination (75, Processor interface: 8-bit Parallel or SPI serial 100, 110, or 120) or external termination 1.8V operation with 3.3V I/O (5V tolerant) High-impedance receive inputs and transmit outputs for no-relay redundancy Industrial operating temperature range Local and remote loopbacks Applications Jitter attenuator with configurable buffer depth, can be inserted into Tx path or Rx path SONET/SDH ADMs, MSPPs, and MSSPs Digital Cross-Connects Receiver automatic receive sensitivity Service Provider Routers adjustment and signal level indication Any carrier-grade telecom equipment with DS1, E1, Receiver LOS, OOF, RAI and AIS status 2048kHz or CC external timing interfaces Transmitter flexible waveform generation Transmitter DSX-1 line build-outs Functional Diagram Transmitter E1 waveforms include G.703 timing from timing to central waveshapes for both 75 coax and 120 BITS/SSU timing IC ZL81000 (DS1, E1, CC, etc.) twisted pair cables timing to Transmitter AIS and alternating ones and zeros timing from BITS/SSU central timing IC generation (DS1, E1, etc.) Transmitter and receiver power-down controls local XO Transmitter and receiver short-circuit detection Transmitter open-circuit detection Internal loopbacks between transmitter and control status receiver for fault detection 1 Microsemi Confidential Copyright 2018. Microsemi Corporation. All Rights Reserved. 1.1.2 PRELIMINARY ZL81000 Data Sheet TABLE OF CONTENTS 1. STANDARDS COMPLIANCE ................................................................................................6 2. BLOCK DIAGRAM .................................................................................................................7 3. DETAILED DESCRIPTION ....................................................................................................7 4. DETAILED FEATURES .........................................................................................................8 4.1 BITS TRANSCEIVER FEATURES ................................................................................................... 8 4.1.1 General ........................................................................................................................................... 8 4.1.2 Receiver ......................................................................................................................................... 8 4.1.3 Transmitter ..................................................................................................................................... 8 4.1.4 Jitter Attenuator .............................................................................................................................. 9 4.2 COMPOSITE CLOCK RECEIVER FEATURES .................................................................................... 9 4.3 GENERAL FEATURES ................................................................................................................... 9 5. PIN DESCRIPTIONS ............................................................................................................ 10 6. FUNCTIONAL DESCRIPTION ............................................................................................. 18 6.1 OVERVIEW ............................................................................................................................... 18 6.2 DEVICE IDENTIFICATION AND PROTECTION ................................................................................. 18 6.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ......................................................... 18 6.4 INPUT CLOCK CONFIGURATION .................................................................................................. 19 6.4.1 Signal Format Configuration ......................................................................................................... 19 6.4.2 Frequency Configuration .............................................................................................................. 19 6.5 INPUT CLOCK QUALITY MONITORING .......................................................................................... 20 6.5.1 Frequency Monitoring ................................................................................................................... 20 6.5.2 Activity Monitoring ........................................................................................................................ 20 6.5.3 Selected Reference Activity Monitoring ........................................................................................ 21 6.5.4 Composite Clock Inputs................................................................................................................ 21 6.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ................................................................ 22 6.6.1 Priority Configuration .................................................................................................................... 22 6.6.2 Automatic Selection Algorithm ..................................................................................................... 22 6.7 DPLL ARCHITECTURE AND CONFIGURATION .............................................................................. 23 6.7.1 DPLL State Machine ..................................................................................................................... 23 6.7.2 Bandwidth ..................................................................................................................................... 23 6.7.3 Damping Factor ............................................................................................................................ 23 6.7.4 Phase Detectors ........................................................................................................................... 24 6.7.5 Loss of Phase Lock Detection ...................................................................................................... 24 6.7.6 Frequency and Phase Measurement ........................................................................................... 25 6.8 OUTPUT CLOCK CONFIGURATION .............................................................................................. 25 6.9 MULTIPROTOCOL BITS TRANSCEIVERS ...................................................................................... 26 6.9.1 Master Clock Connections ........................................................................................................... 27 6.9.2 Receiver Clock Connections ........................................................................................................ 27 6.9.3 Transmitter Clock Connections .................................................................................................... 27 6.9.4 Line Interface Unit ........................................................................................................................ 29 6.9.5 DS1 Synchronization Interface ..................................................................................................... 35 6.9.6 E1 Synchronization Interface ....................................................................................................... 37 6.9.7 G.703 2048kHz Synchronization Interface ................................................................................... 39 6.9.8 G.703 Appendix II 6312kHz Japanese Synchronization Interface ............................................... 40 6.10 COMPOSITE CLOCK RECEIVERS ................................................................................................. 41 6.10.1 IC1A and IC2A Receivers ............................................................................................................ 42 6.11 MICROPROCESSOR INTERFACES ................................................................................................ 44 2 Microsemi Confidential