2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Features DDR2 SDRAM SORDIMM MT18HTS25672RHZ 2GB Figure 1: 200-Pin SORDIMM (R/C B) Features Module height: 30mm (1.181 in) 200-pin, small-outline registered dual in-line mem- ory module (SORDIMM) Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400 2GB (256 Meg x 72) Supports ECC error detection and correction V = 1.8V DD V = 3.03.6V DDSPD JEDEC-standard 1.8V I/O (SSTL 18-compatible) Differential data strobe (DQS, DQS ) option Options Marking 4n-bit prefetch architecture Operating temperature Multiple internal device banks for concurrent opera- Commercial (0C T +70C) None A tion 1 Industrial (40C T +85C) I A Programmable CAS latency (CL) Package Posted CAS additive latency (AL) 200-pin DIMM (Halogen-free) Z t 2 WRITE latency = READ latency - 1 CK Frequency/CL Programmable burst lengths (BL): 4 or 8 2.5 CL = 5 (DDR2-800) -80E 2.5 CL = 6 (DDR2-800) -800 Adjustable data-output drive strength 3.0ns CL = 5 (DDR2-667) -667 64ms, 8192-cycle refresh Notes: 1. Contact Micron for industrial temperature On-die termination (ODT) module offerings. Serial presence detect (SPD) with EEPROM 2. CL = CAS (READ) latency registered mode Phase-lock loop (PLL) to reduce system clock line will add one clock cycle to CL. loading Gold edge contacts Dual rank, using 2Gb TwinDie devices Halogen-free Combination Temp Sensor/EEPROM Table 1: Key Timing Parameters Data Rate (MT/s) t t t Speed Industry RCD RP RC Grade Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) (ns) (ns) -80E PC2-6400 800 800 533 400 12.5 12.5 55 -800 PC2-6400 800 667 533 400 15 15 55 -667 PC2-5300 667 553 400 15 15 55 -53E PC2-4200 553 400 15 15 55 -40E PC2-3200 400 400 15 15 55 PDF: 09005aef83f287c1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 hts18c256x72rhz.pdf - Rev. B 4/14 EN 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Features Table 2: Addressing Parameter 1GB Refresh count 8K Row address 16K A 13:0 Device bank address 8 BA 2:0 Device configuration 2Gb TwinDie (256 Meg x 8) Column address 1K A 9:0 Module rank address 2 S 1:0 Table 3: Part Numbers and Timing Parameters 2GB Modules 1 Base device: MT47H256M8, 2Gb DDR2 TwinDie SDRAM Module Module Memory Clock/ Clock Cycles 2 t t Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP) MT18HTS25672RH(I)Z-80E 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT18HTS25672RH(I)Z-800 2GB 256Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 MT18HTS25672RH(I)Z-667 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 Notes: 1. The data sheet for the base device can be found on Microns Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672RHZ-80EM1. PDF: 09005aef83f287c1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 hts18c256x72rhz.pdf - Rev. B 4/14 EN 2010 Micron Technology, Inc. All rights reserved.