MT48LC16M16A2B4-7E IT:G Micron

256Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC64M4A2 16 Meg x 4 x 4 banks MT48LC32M8A2 8 Meg x 8 x 4 banks MT48LC16M16A2 4 Meg x 16 x 4 banks Options Marking Features Configurations PC100- and PC133-compliant 64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4 Fully synchronous all signals registered on positive 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 edge of system clock 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 Internal, pipelined operation column address can t Write recovery ( WR) be changed every clock cycle t WR = 2 CLK A2 Internal banks for hiding row access/precharge 1 Plastic package OCPL Programmable burst lengths: 1, 2, 4, 8, or full page 1 54-pin TSOP II OCPL (400 mil) TG Auto precharge, includes concurrent auto precharge (standard) and auto refresh modes 1 54-pin TSOP II OCPL (400 mil) P Self refresh mode (not available on AT devices) Pb-free Auto refresh 60-ball TFBGA (x4, x8) (8mm x FB 64ms, 8192-cycle refresh (commercial and 16mm) industrial) 60-ball TFBGA (x4, x8) (8mm x BB 16ms, 8192-cycle refresh (automotive) 16mm) Pb-free LVTTL-compatible inputs and outputs 2 54-ball VFBGA (x16) (8mm x 14 mm) FG Single 3.3V 0.3V power supply 2 54-ball VFBGA (x16) (8mm x 14 mm) BG Pb-free 3 54-ball VFBGA (x16) (8mm x 8 mm) F4 3 54-ball VFBGA (x16) (8mm x 8 mm) B4 Pb-free Timing cycle time 6ns CL = 3 (x8, x16 only) -6A 2 7.5ns CL = 3 (PC133) -75 7.5ns CL = 2 (PC133) -7E Self refresh Standard None 2 4 Low power L , Operating temperature range Commercial (0C to +70C) None Industrial (40C to +85C) IT 4 Automotive (40C to +105C) AT Revision :D/:G 1. Off-center parting line. Notes: 2. Only available on Revision D. 3. Only available on Revision G. 4. Contact Micron for availability. PDF: 09005aef8091e6d1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 256Mb sdr.pdf - Rev. W 05/15 EN 1999 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.256Mb: x4, x8, x16 SDRAM Features Table 1: Key Timing Parameters CL = CAS (READ) latency Clock t t t t Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -6A 167 3-3-3 18 18 18 -75 133 3-3-3 20 20 20 -7E 133 2-2-2 15 15 15 Table 2: Address Table Parameter 64 Meg x 4 32 Meg x 8 16 Meg x 16 Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row addressing 8K A 12:0 8K A 12:0 8K A 12:0 Bank addressing 4 BA 1:0 4 BA 1:0 4 BA 1:0 Column addressing 2K A 9:0 , A11 1K A 9:0 512 A 8:0 Table 3: 256Mb SDR Part Numbering Part Numbers Architecture Package MT48LC64M4A2TG 64 Meg x 4 54-pin TSOP II MT48LC64M4A2P 64 Meg x 4 54-pin TSOP II 1 MT48LC64M4A2FB 64 Meg x 4 60-ball FBGA 1 MT48LC64M4A2BB 64 Meg x 4 60-ball FBGA MT48LC32M8A2TG 32 Meg x 8 54-pin TSOP II MT48LC32M8A2P 32 Meg x 8 54-pin TSOP II 1 MT48LC32M8A2FB 32 Meg x 8 60-ball FBGA 1 MT48LC32M8A2BB 32 Meg x 8 60-ball FBGA MT48LC16M16A2TG 16 Meg x 16 54-pin TSOP II MT48LC16M16A2P 16 Meg x 16 54-pin TSOP II MT48LC16M16A2FG 16 Meg x 16 54-ball FBGA MT48LC16M16A2BG 16 Meg x 16 54-ball FBGA Note: 1. FBGA Device Decoder: www.micron.com/decoder. PDF: 09005aef8091e6d1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 256Mb sdr.pdf - Rev. W 05/15 EN 1999 Micron Technology, Inc. All rights reserved.