MT48LC8M8A2P-75:G Micron

64Mb: x8, x16 SDRAM Features SDR SDRAM MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks Options Marking Features Configuration PC100- and PC133-compliant 8 Meg x 8 (2 Meg x 8 x 4 banks) 8M8 Fully synchronous all signals registered on positive 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16 edge of system clock t Write recovery ( WR) Internal, pipelined operation column address can t 1 WR = 2 CLK A2 be changed every clock cycle 2 Plastic package OCPL Internal banks for hiding row access/precharge 54-pin TSOP II (400 mil) TG Programmable burst lengths: 1, 2, 4, 8, or full page 54-pin TSOP II (400 mil) Pb-free, P Auto precharge, includes concurrent auto precharge RoHS-compliant and auto refresh modes 54-ball VFBGA 8mm x 8mm F4 Self refresh mode (not available on AAT devices) (x16 only) Refresh 3 54-ball VFBGA 8mm x 16mm, Pb- B4 64ms, 4096-cycle refresh (15.6s/row) free, RoHS-compliant (x16 only) (industrial) Timing cycle time 16ms, 4096-cycle refresh (3.9s/row) 6ns CL = 3 (x16 only) -6A (automotive) 7.5ns CL = 3 (PC133) -75 LVTTL-compatible inputs and outputs 7.5ns CL = 2 (PC133) -7E Single 3.3V 0.3V power supply Self refresh AEC-Q100 Standard None PPAP submission Low power L 8D response time Operating temperature range Industrial (40C to +85C) AIT 3 Automotive (40C to +105C) AAT Revision :J 1. See Micron technical note TN-48-05 on Notes: Micron s Web site. 2. Off-center parting line. 3. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Access Time Clock Speed Grade Frequency CL = 2 CL = 3 Setup Time Hold Time -6A 167 MHz 5.5ns 1.5ns 1ns -7E 143 MHz 5.4ns 1.5ns 0.8ns -75 133 MHz 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns 1.5ns 0.8ns -75 100 MHz 6ns 1.5ns 0.8ns 09005aef84942e37 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 64mb ait aat sdr.pdf - Rev. D 6/18 EN 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.64Mb: x8, x16 SDRAM Features Table 2: Address Table Parameter 8 Meg x 8 4 Meg x 16 Configuration 2 Meg x 8 x 4 banks 1 Meg x 16 x 4 banks Refresh count 4K 4K Row addressing 4K A 11:0 4K A 11:0 Bank addressing 4 BA 1:0 4 BA 1:0 Column 512 A 8:0 256 A 7:0 addressing Table 3: 64Mb SDR Part Numbering Part Numbers Architecture Package MT48LC8M8A2TG 8 Meg x 8 54-pin TSOP II MT48LC8M8A2P 8 Meg x 8 54-pin TSOP II MT48LC4M16A2TG 4 Meg x 16 54-pin TSOP II MT48LC4M16A2P 4 Meg x 16 54-pin TSOP II 1 MT48LC4M16A2B4 4 Meg x 16 54-ball VFBGA 1 MT48LC4M16A2F4 4 Meg x 16 54-ball VFBGA Note: 1. FBGA Device Decoder: www.micron.com/decoder. 09005aef84942e37 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 64mb ait aat sdr.pdf - Rev. D 6/18 EN 2011 Micron Technology, Inc. All rights reserved.