74ALVCH16373DGG:11 Nexperia

74ALVCH16373 2.5 V/3.3 V 16-bit D-type transparent latch 3-state Rev. 8 22 November 2021 Product data sheet 1. General description The 74ALVCH16373 is a 16-bit D-type transparent latch with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. This device is fully specified for partial power down applications using I . The I circuitry disables OFF OFF the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels All data inputs have bus hold Latch-up performance exceeds 100 mA per JESD78 Class II Level B Output drive capability 50 transmission lines at 85 C Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Current drive 24 mA at V = 3.0 V CC Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version 74ALVCH16373DGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74ALVCH16373 2.5 V/3.3 V 16-bit D-type transparent latch 3-state 4. Functional diagram 1 24 1 1OE 1EN 48 1LE C1 1OE 2OE 24 2OE 2EN 47 1D0 1Q0 2 25 2LE C4 46 1D1 1Q1 3 44 1D2 1Q2 5 47 2 1D0 3D 1 1Q0 43 1D3 1Q3 6 46 3 1D1 1Q1 41 1D4 1Q4 8 44 5 1D2 1Q2 40 1D5 1Q5 9 43 6 1D3 1Q3 38 1D6 1Q6 11 41 8 1D4 1Q4 37 1D7 1Q7 12 40 9 1D5 1Q5 36 2D0 2Q0 13 38 11 1D6 1Q6 35 2D1 2Q1 14 37 12 1D7 1Q7 33 2D2 2Q2 16 36 13 2D0 4D 2 2Q0 32 2D3 2Q3 17 35 14 2D1 2Q1 30 2D4 2Q4 19 33 16 2D2 2Q2 29 2D5 2Q5 20 32 17 2D3 2Q3 27 2D6 2Q6 22 30 19 2D4 2Q4 26 2D7 2Q7 23 29 20 2D5 2Q5 27 22 1LE 2LE 2D6 2Q6 26 23 2D7 2Q7 48 25 001aam007 001aam009 Fig. 1. Logic symbol Fig. 2. IEC logic symbol V CC data input to internal circuit mna705 Fig. 3. Bus hold circuit 1D0 D Q 1Q0 2D0 D Q 2Q0 LATCH LATCH 1 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels to 7 other channels 001aam010 Fig. 4. Logic diagram 74ALVCH16373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 22 November 2021 2 / 14