74ALVCH16373DGG,51 NXP

74ALVCH16373 2.5 V/3.3 V 16-bit D-type transparent latch 3-state Rev. 7 30 January 2019 Product data sheet 1. General description The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels All data inputs have bus hold Output drive capability 50 transmission lines at 85 C Current drive 24 mA at V = 3.0 V CC 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version 74ALVCH16373DGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74ALVCH16373 2.5 V/3.3 V 16-bit D-type transparent latch 3-state 4. Functional diagram 1 24 1OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 36 2D0 2Q0 13 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 1LE 2LE 48 25 001aam007 Fig. 1. Logic symbol 1 1OE 1EN 48 1LE C1 24 2OE 2EN 25 2LE C4 47 2 1D0 3D 1 1Q0 46 3 1D1 1Q1 44 5 1D2 1Q2 43 6 1D3 1Q3 41 8 1D4 1Q4 40 9 1D5 1Q5 38 11 1D6 1Q6 37 12 1D7 1Q7 36 13 2D0 4D 2 2Q0 35 14 2D1 2Q1 33 16 2D2 2Q2 32 17 2D3 2Q3 30 19 2D4 2Q4 29 20 2D5 2Q5 27 22 2D6 2Q6 26 23 2D7 2Q7 001aam009 Fig. 2. IEC logic symbol 74ALVCH16373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 7 30 January 2019 2 / 15