PSMN0R7-25YLD N-channel 25 V, 0.72 m, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 21 April 2016 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXP s uniqueSchottkyPlu technology delivers high efficiency, low spiking performance usually associated with MOSFETS with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits 100% Avalanche tested at I = 190 A (AS) Ultra low Q , Q and Q for high system efficiency, especially at higher switching G GD OSS frequencies Superfast switching with soft-recovery Low spiking and ringing for low EMI designs UniqueSchottkyPlu technology Schottky-like performance with < 1 A leakage at 25 C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package no glue, no wire bonds, qualified to 150 C Wave solderable exposed leads for optimal visual solder inspection 3. Applications On-board DC:DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage 25 C T 150 C - - 25 V DS j I drain current V = 10 V T = 25 C Fig. 2 1 - - 300 A D GS mb Scan or click this QR code to view the latest information for this product LFPAK56NXP Semiconductors PSMN0R7-25YLD N-channel 25 V, 0.72 m, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit P total power dissipation T = 25 C Fig. 1 - - 158 W tot mb T junction temperature -55 - 150 C j Static characteristics R drain-source on-state V = 4.5 V I = 25 A T = 25 C - 0.76 0.92 m DSon GS D j resistance Fig. 10 V = 10 V I = 25 A T = 25 C - 0.57 0.72 m GS D j Fig. 10 Dynamic characteristics Q total gate charge I = 25 A V = 12 V V = 10 V - 110.2 - nC G(tot) D DS GS Fig. 12 Fig. 13 I = 25 A V = 12 V V = 4.5 V - 50.9 - nC D DS GS Fig. 12 Fig. 13 I = 0 A V = 0 V V = 10 V - 45.8 - nC D DS GS Q gate-drain charge I = 25 A V = 12 V V = 4.5 V - 11.9 - nC GD D DS GS Fig. 12 Fig. 13 Source-drain diode S softness factor I = 25 A dI /dt = -100 A/s V = 0 V - 0.9 - S S GS V = 12 V Fig. 16 DS 1 300A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, Thermal design and operating temperature 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol D 1 S source 2 S source G 3 S source mbb076 S 4 G Gate mb D mounting base connected to drain 1 2 3 4 LFPAK56 Power- SO8 (SOT1023) PSMN0R7-25YLD All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved Product data sheet 21 April 2016 2 / 13