74AHCT1G79GW,165 NXP

74AHC1G79 74AHCT1G79 Single D-type flip-flop positive-edge trigger Rev. 6 23 September 2014 Product data sheet 1. General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: HBM JESD22-A114F: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC1G79GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AHCT1G79GW 74AHC1G79GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74AHCT1G79GV74AHC1G79 74AHCT1G79 NXP Semiconductors Single D-type flip-flop positive-edge trigger 4. Marking Table 2. Marking codes 1 Type number Marking 74AHC1G79GW AP 74AHC1G79GV A79 74AHCT1G79GW CP 74AHCT1G79GV C79 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 4 4 QD P Q P Fig 1. Logic symbol Fig 2. IEC logic symbol & & & & 7* 7* 4 & & & & 7* 7* & & D P Q Fig 3. Logic diagram 74AHC AHCT1G79 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 6 23 September 2014 2 of 13 &3 D &3 &3