PSMN2R4-30YLD NXP

PSMN2R4-30YLD N-channel 30 V, 2.4 m logic level MOSFET in LFPAK56 using NextPowerS3 Technology 7 February 2014 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXPs unique SchottkyPlus technology delivers high efficiency, low spiking performance usually associated with MOSFETs with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits Ultra low Q , Q and Q for high system efficiency, especially at higher switching G GD OSS frequencies Superfast switching with soft-recovery s-factor > 1 Low spiking and ringing for low EMI designs Unique SchottkyPlus technology Schottky-like performance with < 1A leakage at 25 C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package no glue, no wire bonds, qualified to 175 C Wave solderable exposed leads for optimal visual solder inspection 3. Applications On-board DC-to-DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage 25 C T 175 C - - 30 V DS j I drain current T = 25 C V = 10 V Fig. 2 1 - - 100 A D mb GS P total power dissipation T = 25 C Fig. 1 - - 106 W tot mb Scan or click this QR code to view the latest information for this product LFPAK56NXP Semiconductors PSMN2R4-30YLD N-channel 30 V, 2.4 m logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit T junction temperature -55 - 175 C j Static characteristics R drain-source on-state V = 4.5 V I = 25 A T = 25 C - 2.7 3.1 m DSon GS D j resistance Fig. 10 V = 10 V I = 25 A T = 25 C - 2 2.4 m GS D j Fig. 10 Dynamic characteristics Q gate-drain charge V = 4.5 V I = 25 A V = 15 V - 4.3 - nC GD GS D DS Fig. 12 Fig. 13 Q total gate charge V = 4.5 V I = 25 A V = 15 V - 16.2 - nC G(tot) GS D DS Fig. 12 Fig. 13 Source-drain diode S softness factor I 25 A V = 0 V dI /dt = -100 A/s - 1 - S GS S V = 15 V Fig. 15 DS 1 Continuous current is limited by package 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source mb D 2 S source G 3 S source mbb076 S 4 G gate 1 2 3 4 mb D mounting base connected to LFPAK56 Power- drain SO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN2R4-30YLD LFPAK56 Plastic single-ended surface-mounted package (LFPAK56 SOT669 Power-SO8 Power-SO8) 4 leads PSMN2R4-30YLD All information provided in this document is subject to legal disclaimers. NXP N.V. 2014. All rights reserved Product data sheet 7 February 2014 2 / 13