ASM3P2182AF-08SR ON Semiconductor

ASM3P2182A LCD Panel EMI Reduction IC Features The ASM3P2182A reduces electromagnetic interference (EMI) at the clock source, allowing system wide FCC approved method of EMI attenuation. reduction of EMI of down stream clock and data Provides up to 15dB EMI reduction. dependent signals. The ASM3P2182A allows significant Generates a 1X low EMI spread spectrum clock of system cost savings by reducing the number of circuit the input frequency. board layers ferrite beads, shielding and other passive Input frequency range: 25MHz to 210MHz. components that are traditionally required to pass EMI Internal loop filter minimizes external components regulations. and board space. The ASM3P2182A uses the most efficient and optimized Center spread. modulation profile approved by the FCC and is 4 spread frequency deviation selections: 0.13% to implemented in a proprietary all digital method. 1.24%. Low inherent Cycle-to-cycle jitter. The ASM3P2182A modulates the output of a single PLL in order to spread the bandwidth of a synthesized 3.3V Operating Voltage. clock, and more importantly, decreases the peak TTL or CMOS compatible inputs and outputs. amplitudes of its harmonics. This results in significantly Low power CMOS design. lower system EMI compared to the typical narrow band Supports notebook VGA and other LCD timing signal produced by oscillators and most frequency controller applications. generators. Lowering EMI by increasing a signals Available in 8-pin SOIC Package. bandwidth is called spread spectrum clock generation. Product Description Applications The ASM3P2182A is a versatile spread spectrum The ASM3P2182A is targeted towards EMI management frequency modulator designed specifically for a wide for memory and LVDS interfaces in mobile graphic range of input clock frequencies from 25MHz to 210MHz. chipsets and high-speed digital applications such as PC (Refer to Input Frequency and Modulation Rate Table). peripheral devices, consumer electronics, and The ASM3P2182A can generate an EMI reduced clock embedded controller systems. from an OSC or a system generated clock. The ASM3P2182A offers a Center Spread clock and with a percentage deviation from 0.13% or 1.24%. V DD S0 FS0 FS1 PLL Modulation CLKIN Crystal Frequency Oscillato Divider Phase Loop Output r VCO Detector Filter Divider Feedback Divider ModOUT VSS 2010 SCILLC. All rights reserved. Publication Order Number: OCTOBER 2010 Rev. 2.1 ASM3P2182/D ASM3P2182A Pin Configuration CLKIN FS1 1 8 FS0 GND 2 7 ASM3P2182A VDD S1 6 3 5 ModOUT S0 4 Pin Description Pin Pin Name Type Description 1 CLKIN I Connect to externally generated clock signal. 2 GND P Ground to entire chip. Spread range select. Digital logic input used to select frequency deviation 3 S1 I (Refer to Spread Deviation Table). This pin has an internal pull-up resistor. Spread range select. Digital logic input used to select frequency deviation 4 S0 I (Refer to Spread Deviation Table). This pin has an internal pull-up resistor. 5 ModOUT O Spread spectrum low EMI output. 6 VDD P Power supply for the entire chip (3.3V). Frequency range select. Digital logic input used to select frequency range 7 FS0 I (Refer to Input Frequency and Modulation Rate Table). This pin has an internal pull-up resistor. Frequency range select. Digital logic input used to select frequency range 8 FS1 I (Refer to Input Frequency and Modulation Rate Table). This pin has an internal pull-up resistor. Input Frequency and Modulation Rate table FS1 (pin 8) FS0 (pin 7) Frequency Range 0 0 25MHz to 50MHz 0 1 50MHz to 103MHz 1 0 75MHz to 150MHz 1 1 160MHz to 210MHz Rev. 2 Page 2 of 6 www.onsemi.com