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FDG1024NZ Dual N-Channel Power Trench MOSFET June 2010 FDG1024NZ Dual N-Channel PowerTrench MOSFET 20 V, 1.2 A, 175 m Features General Description Max r = 175 m at V = 4.5 V, I = 1.2 A This dual N-Channel logic level enhancement mode field effect DS(on) GS D transistors are produced using Fairchilds proprietary, high cell Max r = 215 m at V = 2.5 V, I = 1.0 A DS(on) GS D density, DMOS technology. This very high density process is Max r = 270 m at V = 1.8 V, I = 0.9 A especially tailored to minimize on-state resistance. This device DS(on) GS D has been designed especially for low voltage applications as a Max r = 389 m at V = 1.5 V, I = 0.8 A DS(on) GS D replacement for bipolar digital transistors and small signal HBM ESD protection level >2 kV (Note 3) MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with Very low level gate drive requirements allowing operation in different bias resistor values. 1.5 V circuits (V < 1 V) GS(th) Very small package outline SC70-6 RoHS Compliant S2 G2 S1 D1 1 6 D1 G1 2 5 G2 D2 G1 D2 3 4 S2 S1 SC70-6 MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Ratings Units V Drain to Source Voltage 20 V DS V Gate to Source Voltage 8 V GS -Continuous T = 25C (Note 1a) 1.2 A I A D -Pulsed 6 Power Dissipation T = 25C (Note 1a) 0.36 A P W D Power Dissipation T = 25C (Note 1b) 0.30 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics R Thermal Resistance, Junction to Ambient (Note 1a) 350 JA C/W R Thermal Resistance, Junction to Ambient (Note 1b) 415 JA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity .4N FDG1024NZ SC70-6 7 8 mm 3000 units 1 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FDG1024NZ Rev.C