HUFA75344S3 Data Sheet May 2013 75A, 55V, 0.008 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Thermal Impedance PSPICE and SABER Models achieves the lowest possible on-resistance per silicon area, Available on the web at: www.fairchildsemi.com resulting in outstanding performance. This device is capable Peak Current vs Pulse Width Curve of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored UIS Rating Curve charge. It was designed for use in applications where power Related Literature efficiency is important, such as switching regulators, - TB334, Guidelines for Soldering Surface Mount switching converters, motor drivers, relay drivers, low- Components to PC Boards voltage bus switches, and power management in portable and battery-operated products. Symbol Formerly developmental type TA75344. D Ordering Information PART NUMBER PACKAGE BRAND G HUFA75344S3 TO-262AA 75344S NOTE: When ordering, use the entire part number. Add the suffix T to S obtain the TO-262AA variant in tape and reel, e.g., HUFA75344S3. Packaging SOURCE DRAIN GATE DRAIN TO-262AA (FLANGE) This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: HUFA75344S3 o Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified C UNITS Drain to Source Voltage (Note 1) . V 55 V DSS Drain to Gate Voltage (R = 20k ) (Note 1) . V 55 V GS DGR Gate to Source Voltage . V 20 V GS Drain Current Continuous (Figure 2) . I 75 A D Pulsed Drain Current I Figure 4 DM Pulsed Avalanche Rating E Figure 6 AS Power Dissipation P 285 W D o o Derate Above 25 C 1.90 W/ C o Operating and Storage Temperature . T , T -55 to 175 C J STG Maximum Temperature for Soldering o Leads at 0.063in (1.6mm) from Case for 10s .T 300 C L o Package Body for 10s, See Techbrief 334 . T 260 C pkg CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: o o 1. T = 25 C to 150 C. J o Electrical Specifications T = 25 C, Unless Otherwise Specified C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BV I = 250 A, V = 0V (Figure 11) 55 - - V DSS D GS Zero Gate Voltage Drain Current I V = 50V, V = 0V - - 1 A DSS DS GS o V = 45V, V = 0V, T = 150C- -250 A DS GS C Gate to Source Leakage Current I V = 20V - - 100 nA GSS GS ON STATE SPECIFICATIONS Gate to Source Threshold Voltage V V = V , I = 250 A (Figure 10) 2 - 4 V GS(TH) GS DS D Drain to Source On Resistance r I = 75A, V = 10V (Figure 9) - 6.5 8.0 m DS(ON) D GS THERMAL SPECIFICATIONS o Thermal Resistance Junction to Case R (Figure 3) - - 0.52 C/W JC o Thermal Resistance Junction to Ambient R JA TO-262 - - 62 C/W SWITCHING SPECIFICATIONS (V = 10V) GS Turn-On Time t V = 30V, I 75A, -- 187 ns ON DD D R = 0.4 , V = 10V, L GS Turn-On Delay Time t -13 - ns d(ON) R = 3.0 GS Rise Time t - 125 - ns r Turn-Off Delay Time t -46 - ns d(OFF) Fall Time t -57 - ns f Turn-Off Time t -- 147 ns OFF GATE CHARGE SPECIFICATIONS Total Gate Charge Q V = 0V to 20V V = 30V, - 175 210 nC g(TOT) GS DD I 75A, D Gate Charge at 10V Q V = 0V to 10V - 90 108 nC g(10) GS R = 0.4 L Threshold Gate Charge Q V = 0V to 2V - 5.9 7.0 nC g(TH) GS I = 1.0mA g(REF) Gate to Source Gate Charge Q -14 - nC (Figure 13) gs Reverse Transfer Capacitance Q -39 - nC gd CAPACITANCE SPECIFICATIONS Input Capacitance C V = 25V, V = 0V, - 3200 - pF ISS DS GS f = 1MHz Output Capacitance C - 1170 - pF OSS (Figure 12) Reverse Transfer Capacitance C - 310 - pF RSS 2013 Fairchild Semiconductor Corporation HUFA75344S3 Rev. B4