MC10EL31, MC100EL31
5 V ECL D FlipFlop
With Set and Reset
Description
The MC10EL/100EL31 is a D flip-flop with set and reset. The
device is functionally equivalent to the E131 device with higher www.onsemi.com
performance capabilities. With propagation delays and output
transition times significantly faster than the E131, the EL31 is ideally
suited for those applications which require the ultimate in AC
performance.
8
8
Both set and reset inputs are asynchronous, level triggered signals.
1
1
Data enters the master portion of the flip-flop when clock is LOW and
is transferred to the slave, and thus the outputs, upon a positive SOIC8 NB TSSOP8
D SUFFIX DT SUFFIX
transition of the clock.
CASE 75105 CASE 948R02
The 100 Series contains temperature compensation.
Features
MARKING DIAGRAMS*
475 ps Propagation Delay
2.8 GHz Toggle Frequency
8 8
ESD Protection:
HEL31
HL31
> 1 kV Human Body Model
ALYW
ALYW
> 100 V Machine Model
1
PECL Mode Operating Range: V = 4.2 V to 5.7 V 1
CC
with V = 0 V
EE
8
NECL Mode Operating Range: V = 0 V 8
CC
with V = 4.2 V to 5.7 V KEL31
EE
KL31
ALYW
ALYW
Internal Input Pulldown Resistors on D, CLK, S, and R
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1
1
Moisture Sensitivity:
Level 1 for SOIC8 NB SOIC8 NB TSSOP8
Level 3 for TSSOP8
For Additional Information, see Application Note AND8003/D
H = MC10
Flammability Rating: UL 94 V0 @ 0.125 in, K = MC100
A = Assembly Location
Oxygen Index: 28 to 34
L = Wafer Lot
Metastability 125 ps (see Application Note AN1504)
Y = Year
Transistor Count = 79 Devices W = Work Week
= Pb-Free Package
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 7 MC10EL31/DMC10EL31, MC100EL31
Table 1. TRUTH TABLE
S 1 8 V
CC D S* R* CLK Q
L L L Z L
S H L L Z H
D 2 Q X H L X H
7
D
X L H X L
X H H X Undef
Z = LOW to HIGH Transition
CLK 3 6 Q
* Pins will default low when left open.
R
Table 2. PIN DESCRIPTION
PIN FUNCTION
R45 V
EE
S ECL Set Input
D ECL Data Input
Figure 1. Logic Diagram and Pinout Assignment
R ECL Reset Input
CLK ECL Clock Input
Q, Q ECL Data Outputs
V Positive Supply
CC
V Negative Supply
EE
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V PECL Mode Power Supply- V = 0 V 8 V
CC EE
V NECL Mode Power Supply V = 0 V 8 V
EE CC
V PECL Mode Input Voltage V = 0 V V V 6 V
I EE I CC
NECL Mode Input Voltage V V 6
V = 0 V I EE
CC
I Output Current Continuous 50 mA
out
Surge
100
T Operating Temperature Range 40 to +85 C
A
T Storage Temperature Range 65 to +150 C
stg
Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W
JA
SOIC8 NB 130
500 lfpm
Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 C/W
JC
Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W
JA
TSSOP8 140
500 lfpm
Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W
JC
T Wave Solder (Pb-Free) < 2 to 3 sec @ 260C 265 C
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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