MC100EL39
5 V ECL 2/4, 4/6 Clock
Generation Chip
Description
The MC100EL39 is a low skew 2/4, 4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
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output edges are all precisely aligned.
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V may also rebias AC coupled inputs. When used, decouple V
BB BB
and V via a 0.01 F capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
SOIC20 WB
already in the LOW state. This avoids any chance of generating a runt
DW SUFFIX
clock pulse on the internal clock when the device is enabled/disabled
CASE 751D05
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
MARKING DIAGRAM*
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL39s, the Master Reset
20
(MR) input must be asserted to ensure synchronization. For systems
which only use one EL39, the MR pin need not be exercised as the
100EL39
internal divider design ensures synchronization between the 2/4 and
AWLYYWWG
the 4/6 outputs of a single device.
Features
1
50 ps Output-to-Output Skew
Synchronous Enable/Disable
A = Assembly Location
Master Reset for Synchronization
WL = Wafer Lot
ESD Protection: YY = Year
WW = Work Week
> 2 kV Human Body Model
G = Pb-Free Package
> 100 V Machine Model
The 100 Series Contains Temperature Compensation
*For additional marking information, refer to
PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V
Application Note AND8002/D.
CC EE
NECL Mode Operating Range:
V = 0 V with V = 4.2 V to 5.7 V
CC EE
Internal Input Pulldown Resistors on EN, MR, CLK(s), and
DIVSEL(s)
ORDERING INFORMATION
Q Output will Default LOW with Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Device Package Shipping
Moisture Sensitivity: Level 3 (Pb-Free) SOIC20 WB 1000 Tape & Reel
MC100EL39DWR2G
(Pb-Free)
(For Additional Information, see Application Note AND8003/D)
For information on tape and reel specifications, in-
Flammability Rating: UL 94 V0 @ 0.125 in,
cluding part orientation and tape sizes, please refer
Oxygen Index 28 to 34
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Transistor Count = 419 Devices
This Device is Pb-Free, Halogen Free and is RoHS Compliant
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 8 MC100EL39/DMC100EL39
V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V
CC EE
Table 1. PIN DESCRIPTION
20 19 18 17 16 15 14 13 12
11
Pin Function
CLK, CLK ECL Diff Clock Inputs
EN ECL Sync Enable
MR ECL Master Reset
Q0, Q0; Q1, Q1 ECL Diff 2/4 Outputs
Q2, Q2; Q3, Q3 ECL Diff 4/6 Outputs
1 2 3 4 567 8 9 10
DIVSELa, ECL Frequency Select Input
V EN CLK CLK V MR V
NC DIVSELb ECL Frequency Select Input
CC BB CC
V Reference Voltage Output
BB
V Positive Supply
CC
V Negative Supply
EE
NC No Connect
NOTE: All V pins are tied together on the die.
CC
Warning: All V and V pins must be externally connected to
CC EE
Power Supply to guarantee proper operation.
Figure 1. Pinout: SOIC-20 (Top View)
Table 2. FUNCTION TABLE
Function CLK* EN* MR*
DIVSELa
Divide Z L L
Q0
Hold Q ZZ H L
0 3
CLK P2/4
Reset Q X X H
0 3
Q0
R
CLK
Z = Low-to-High Transition
Q1
ZZ = High-to-Low Transition
*Pin will default low when left open.
Q1
Q2
DIVSELa** Q , Q Outputs
EN
0 1
P4/6
0 Divide by 2
Q2
R
1 Divide by 4
Q3
DIVSELb** Q , Q Outputs
2 3
MR
Q3
0 Divide by 4
1 Divide by 6
DIVSELb
**Pin will default low when left open.
Figure 2. Logic Diagram
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2
DIVSELb
DIVSELa