MC100EL35DTG ON Semiconductor

MC10EL35, MC100EL35 5 V ECL JK FlipFlop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition www.onsemi.com of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. 8 8 1 1 Features SOIC8 NB TSSOP8 525 ps Propagation Delay D SUFFIX DT SUFFIX 2.2G Hz Toggle Frequency CASE 75105 CASE 948R02 ESD Protection: > 1 kV Human Body Model > 100 V Machine Model MARKING DIAGRAMS* PECL Mode Operating Range: V = 4.2 V to 5.7 with V = 0 V CC EE 8 8 NECL Mode Operating Range: V = 0 V with CC HEL35 HL35 V = 4.2 V to 5.7 V EE ALYW ALYW Internal Input Pulldown Resistors on J, K, CLK, and R 1 1 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: 8 8 Level 1 for SOIC8 NB KEL35 KL35 Level 3 for TSSOP8 ALYW ALYW For Additional Information, see Application Note AND8003/D 1 Flammability Rating: UL94 V0 0.125 in, 1 Oxygen Index 28 to 34 SOIC8 TSSOP8 Transistor Count = 81 Devices H = MC10 These Devices are Pb-Free, Halogen Free and are RoHS Compliant K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC10EL35DG SOIC8 NB 98 Units / Tube (Pb-Free) MC10EL35DTG TSSOP8 100 Unit / Tube (Pb-Free) MC100EL35DG SOIC8 NB 98 Units / tube (Pb-Free) MC100EL35DTG TSSOP8 100 Units / Tube (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC10EL35/DMC10EL35, MC100EL35 Table 1. PIN DESCRIPTION J 1 8 V CC J PIN FUNCTION J ECL Input K ECL Input 2 7 Q K K R ECL Reset CLK ECL Clock Input CLK 3 6 Q Q, Q ECL Data Outputs V Positive Supply CC R V Negative Supply EE R45 V EE Table 1. TRUTH TABLE Figure 1. Logic Diagram and Pinout Assignment J* K* R* CLK Qn+1 L L L Z Qn L H L Z L H L L Z H H H L Z Qn X X H X L Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W JA 500 lfpm SOIC8 NB 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm TSSOP8 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2