MC100EL38 5 VECL 2, 4/6 Clock Generation Chip Description The MC100EL38 is a low skew 2, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common www.onsemi.com output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB SOIC20 WB V may also rebias AC coupled inputs. When used, decouple V BB BB DW SUFFIX and V via a 0.01 F capacitor and limit current sourcing or sinking CC CASE 751D05 to 0.5 mA. When not used, V should be left open. BB The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is MARKING DIAGRAM* already in the LOW state. This avoids any chance of generating a runt 20 clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider 100EL38 AWLYYWWG stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. 1 The Phase Out output will go HIGH for one clock cycle whenever A = Assembly Location the 2 and the 4/6 outputs are both transitioning from a LOW to a WL = Wafer Lot HIGH. This output allows for clock synchronization within the system. YY = Year Upon startup, the internal flip-flops will attain a random state WW = Work Week therefore, for systems which utilize multiple EL38s, the master reset G = Pb-Free Package (MR) input must be asserted to ensure synchronization. For systems which only use one EL38, the MR pin need not be exercised as the *For additional marking information, refer to Application Note AND8002/D. internal divider design ensures synchronization between the 2 and the 4/6 outputs of a single device. 50 ps Output-to-Output Skew ORDERING INFORMATION Synchronous Enable/Disable Device Package Shipping Master Reset for Synchronization MC100EL38DWR2G SOIC20 WB 1000/Tape & Reel ESD Protection: (Pb-Free) 2 kV Human Body Model 100 V Machine Model For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer The 100 Series Contains Temperature Compensation to our Tape and Reel Packaging Specifications PECL Mode Operating Range: Brochure, BRD8011/D. V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: Moisture Sensitivity Level: 3 (Pb-Free) V = 0 V with V = 4.2 V to 5.7 V For Additional Information, see Application Note CC EE AND8003/D Internal 75 k Input Pulldown Resistors on CLK, EN, MR, and DIVSEL Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Q Output will Default LOW with Inputs Open or at V Transistor Count = 388 devices EE Meets or Exceeds JEDEC Spec EIA/JESD78 IC These Devices are Pb-Free, Halogen Free and are Latchup Test RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 9 MC100EL38/DMC100EL38 V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V CC EE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 678 9 10 V EN DIV SEL CLK CLK V MR V Phase Out Phase Out CC BB CC * All V pins are tied together on the die. CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. Pinout Assignment (Top View) Q0 CLK P2 Q0 R CLK Q1 Q1 Q2 EN R P4/6 Q2 R Q3 MR Q3 DIVSEL PHASE OUT Phase Out PHASE OUT Logic R Figure 2. Logic Diagram Table 1. PIN DESCRIPTION Table 2. FUNCTION TABLE Pin Function CLK EN MR Function CLK, CLK ECL Diff Clock Inputs Z L L Divide ZZ H L Hold Q 0 3 Q , Q Q , Q ECL Diff 2 Outputs 0 1 0 1 X X H Reset Q 0 3 Q , Q Q , Q ECL Diff 4/6 Outputs 2 3 2 3 Z = Low-to-High Transition ZZ = High-to-Low Transition EN ECL Sync Enable Input X = Dont Care MR ECL Master Reset Input DIVSEL ECL Frequency Select Input DIVSEL Q , Q OUTPUTS 2 3 Phase Out, Phase Out ECL Phase Sync Diff. Signal Output L Divide by 4 H Divide by 6 V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE www.onsemi.com 2