MC10EL34, MC100EL34 5 VECL 2, 4, 8 Clock Generation Chip Description The MC10/100EL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The www.onsemi.com internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V pin, an internally BB generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is 16 connected to V as a switching reference voltage. V may also BB BB 1 rebias AC coupled inputs. When used, decouple V and V via a BB CC 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. SOIC16 When not used, V should be left open. BB D SUFFIX The common enable (EN) is synchronous so that the internal CASE 751B05 dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled MARKING DIAGRAMS* as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider 16 stages. The internal enable flipflop is clocked on the falling edge of the input clock, therefore, all associated specification limits are 10EL34G referenced to the negative edge of the clock input. AWLYWW Upon startup, the internal flip-flops will attain a random state the 1 master reset (MR) input allows for the synchronization of the internal 16 dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation. 100EL34G AWLYWW Features 1 50 ps Output-to-Output Skew A = Assembly Location Synchronous Enable/Disable WL = Wafer Lot Master Reset for Synchronization YY = Year WW = Work Week PECL Mode Operating Range: G = Pb-Free Package V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: *For additional marking information, refer to Application Note AND8002/D. V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input 75 k Pulldown Resistors on CLK(s), EN, and MR These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Device Package Shipping MC10EL34DG SOIC16 48 Units/Tube Pb-Free) MC100EL34DG SOIC16 48 Units/Tube (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 11 MC10EL34/DMC10EL34, MC100EL34 V EN NC CLK CLK V MR V CC BB EE Table 1. FUNCTION TABLE 16 15 14 13 12 11 10 9 CLK* EN* MR* Function Z L L Divide D QR ZZ H L Hold Q 0 3 X X H Reset Q 0 3 *Pins will default low when left open. 2 4 8 QR QR QR Z = Low-to-High Transition ZZ = High-to-Low Transition 2 3 56 8 1 4 7 Table 2. PIN DESCRIPTION Q0 V Q1 V Q2 Q0 Q1 CC Q2 CC Pin Function *All V pins are tied together on the die. CC CLK, CLK ECL Diff Clock Inputs Warning: All V and V pins must be externally connected CC EE EN ECL Sync Enable to Power Supply to guarantee proper operation. MR ECL Master Reset Figure 1. Logic Diagram and Pinout Assignment Q0, Q0 ECL Diff 2 Outputs Q1, Q1 ECL Diff 4 Outputs Q2, Q2 ECL Diff 8 Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE NC No Connect Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 K Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 1 KV Machine Model > 100 V Charge Device Model > 2 KV Moisture Sensitivity (Note 1) Level 1 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 191 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. www.onsemi.com 2