MC100EP809FAG ON Semiconductor

3.3 V2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable MC100EP809 www.onsemi.com Description The MC100EP809 is a low skew 2:1:9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage 32 1 applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are QFN32 MN SUFFIX one differential HSTL and one differential LVPECL. Both input pairs CASE 488AM can accept LVDS levels. They are selected by the CLK SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, MARKING DIAGRAM* is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (Figure 8). 1 The MC100EP809 guarantees low outputtooutput skew. The MC100 optimal design, layout, and processing minimize skew within a device EP809 and from lot to lot. The MC100EP809 output structure uses open AWLYYWW emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration (Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is A = Assembly Location WL = Wafer Lot being used. If an output pair is unused, both outputs may be left open YY = Year (unterminated) without affecting skew. WW = Work Week Designers can take advantage of the EP809s performance to = PbFree Package distribute low skew clocks across the backplane of the board. Both (Note: Microdot may be in either location) clock inputs may be singleend driven by biasing the nondriven pin in an input pair (Figure 7). *For additional marking information, refer to Application Note AND8002/D. Features 100 ps Typical DevicetoDevice Skew 15 ps Typical within Device Skew ORDERING INFORMATION HSTL Compatible Outputs Drive 50 to GND with no Device Package Shipping Offset Voltage MC100EP809MNG QFN32 74 Units / Rail Maximum Frequency > 750 MHz (PbFree) 850 ps Typical Propagation Delay Fully Compatible with Micrel SY89809L PECL and HSTL Mode Operating Range: V = 3 V to 3.6 V CCI with GND = 0 V, V = 1.6 V to 2.0 V CCO Open Input Default State This Device is PbFree and is RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: March, 2021 Rev. 11 MC100EP809/DV V CCO CCO Q2 Q6 Q2 Q6 Q1 Q7 Q1 Q7 Q0 Q8 Q0 Q8 V CCO V CCO MC100EP809 Exposed Pad (EP) 32 31 30 29 28 27 26 25 V CCI 1 24 V CCO HSTL CLK 2 23 Q3 HSTL CLK 22 3 Q3 CLK SEL 4 21 Q4 MC100EP809 LVPECL CLK 5 20 Q4 LVPECL CLK 6 19 Q5 GND 7 18 Q5 OE 8 17 V CCO 9 10 11 12 13 14 15 16 Figure 1. 32 Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE PIN FUNCTION OE* CLK SEL Q0 Q8 Q0 Q8 HSTL CLK*, HSTL or LVDS Differential Inputs L L L H HSTL CLK** L H L H LVPECL CLK*, LVPECL or LVDS Differential Inputs H L HSTL CLK HSTL CLK LVPECL CLK** H H LVPECL CLK LVPECL CLK CLK SEL** LVCMOS/LVTTL Input CLK Select *The OE (Output Enable) signal is synchronized with the rising edge OE** LVCMOS/LVTTL Output Enable of the HSTL CLK and LVOCL CLK signals. Q0 Q8, HSTL Differential Outputs Q0 Q8 V Positive Supply Core CC1 (3.0 V 3.6 V) V Positive Supply HSTL Outputs CC0 (1.6 V 2.0 V) GND Ground EP The exposed pad (EP) on the QFN32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to GND. * Pins will default LOW when left open. ** Pins will default HIGH when left open. www.onsemi.com 2