MC100EP809
3.3V2:1:9 Differential
HSTL/PECL/LVDS to HSTL
Clock Driver with LVTTL
Clock Select and Enable
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Description
MARKING
The MC100EP809 is a low skew 2:1:9 differential clock driver,
DIAGRAMS*
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
MC100
aligned low skew signals to their destination. The two clock inputs are
EP809
one differential HSTL and one differential LVPECL. Both input pairs
32LEAD LQFP
AWLYYWWG
can accept LVDS levels. They are selected by the CLK_SEL pin
FA SUFFIX
which is LVTTL. To avoid generation of a runt clock pulse when the
32
CASE 873A
device is enabled/disabled, the Output Enable (OE), which is LVTTL,
1
is synchronous ensuring the outputs will only be enabled/disabled
when they are already in LOW state (Figure 9).
1
The MC100EP809 guarantees low outputtooutput skew. The
MC100
optimal design, layout, and processing minimize skew within a device
EP809
32
1
and from lot to lot. The MC100EP809 output structure uses open
AWLYYWW
emitter architecture and will be terminated with 50 to ground
QFN32
MN SUFFIX
instead of a standard HSTL configuration (Figure 7). To ensure the
CASE 488AM
tight skew specification is realized, both sides of the differential output
need to be terminated identically into 50 even if only one output is
A = Assembly Location
being used. If an output pair is unused, both outputs may be left open
WL = Wafer Lot
(unterminated) without affecting skew.
YY = Year
Designers can take advantage of the EP809s performance to
WW = Work Week
distribute low skew clocks across the backplane of the board. Both
G or = PbFree Package
clock inputs may be singleend driven by biasing the nondriven pin
(Note: Microdot may be in either location)
in an input pair (Figure 8).
*For additional marking information, refer to
Application Note AND8002/D.
Features
100 ps Typical DevicetoDevice Skew
ORDERING INFORMATION
15 ps Typical within Device Skew
See detailed ordering and shipping information in the package
HSTL Compatible Outputs Drive 50 to GND with no
dimensions section on page 8 of this data sheet.
Offset Voltage
Maximum Frequency > 750 MHz
850 ps Typical Propagation Delay
Fully Compatible with Micrel SY89809L
PECL and HSTL Mode Operating Range: V = 3 V to 3.6 V
CCI
with GND = 0 V, V = 1.6 V to 2.0 V
CCO
Open Input Default State
These Devices are PbFree and are RoHS Compliant
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
April, 2015 Rev. 10 MC100EP809/D24 23 22 21 20 19 18 17
V
V
CCO
V 25 16 V CCO
CCO CCO
Q2
26 15
Q2 Q6
Q6
Q2
27 14
Q2 Q6
Q6
Q1
Q1 28 13 Q7
Q7
Q1
29 12 Q7
Q1
Q7
Q0
30 11
Q0 Q8
Q8
Q0
31 10
Q0 Q8
Q8
V
CCO
V 32 9 V
CCO
CCO V
CCO
12 345678
MC100EP809
V
V CCO
CCI
Q3
HSTL_CLK
Q3
HSTL_CLK
CLK_SEL Q4
MC100EP809
Q4
LVPECL_CLK
Q5
LVPECL_CLK
Q5
GND
V
OE CCO
All V , V , and GND pins must be externally connected to
CCI CCO
appropriate Power Supply to guarantee proper operation (V V ).
CCI CCO
Figure 1. 32Lead LQFP Pinout (Top View)
Exposed Pad
(EP)
32 31 30 29 28 27 26 25
V
CCI 1 24
V
CCO
HSTL_CLK
2 23
Q3
HSTL_CLK 22
3
Q3
CLK_SEL
4 21
Q4
MC100EP809
LVPECL_CLK
5 20
Q4
LVPECL_CLK 6
19
Q5
GND 7
18
Q5
OE 8 17
V
CCO
9 10 11 12 13 14 15 16
Figure 2. 32Lead QFN Pinout (Top View)
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2