3.3 VECL 2:8 Differential Fanout Buffer MC100LVE310 Description The MC100LVE310 is a low voltage, low skew 2:8 differential ECL www.onsemi.com fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 , even if PLCC28 FN SUFFIX only one side is being used. In most applications all eight differential CASE 776 pairs will be used and therefore terminated. In the case where fewer than eight pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain MARKING DIAGRAM* minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 1020 ps) of the 1 outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate MC100LVE310G outputs from one another such that the guideline expressed above AWLYYWW holds only for outputs on the same side of the package. The MC100LVE310, as with most ECL devices, can be operated from a positive V supply in LVPECL mode. This allows the CC LVE310 to be used for high performance clock distribution in +3.3 V A = Assembly Location systems. Designers can take advantage of the LVE310s performance WL = Wafer Lot to distribute low skew clocks across the backplane or the board. In YY = Year aPECL environment series or Thevenin line terminations are WW = Work Week typically used as they require no additional power supplies, if parallel G = Pb-Free Package termination is desired a terminating voltage of V 2.0 V will need CC *For additional marking information, refer to to be provided. For more information on using PECL, designers Application Note AND8002/D. should refer to Application Note AN1406/D. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused ORDERING INFORMATION differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB Device Package Shipping and V via a 0.01 F capacitor and limit current sourcing or sinking CC MC100LVE310FNR2G PLCC28 500 Tape & Reel to 0.5 mA. When not used, V should be left open. BB (Pb-Free) Features For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer 200 ps Part-to-Part Skew to our Tape and Reel Packaging Specifications 50 ps Output-to-Output Skew Brochure, BRD8011/D. PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 3.0 V to 3.8 V CC EE Q Output will Default LOW with All Inputs Open or at V EE The 100 Series Contains Temperature Compensation These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 7 MC100LVE310/DMC100LVE310 Q0 Q0 Q1 V Q1 Q2 Q2 CCO Q0 Q0 25 24 23 22 21 20 19 Q1 V 26 18 Q3 EE Q1 Q3 CLK SEL 27 17 Q2 Q4 Q2 CLKa 28 16 CLKa Q3 Pinout: 28-Lead PLCC V 15 V CC 1 CLKa CCO Q3 (Top View) CLKb CLKa 2 14 Q4 Q4 CLKb Q4 3 13 Q5 V BB Q5 CLK SEL CLKb 4 12 Q5 Q5 5 6 789 10 11 Q6 Q6 CLKb NC Q7 V Q7 Q6 Q6 CCO Q7 Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Q7 Figure 1. Logic Diagram and Pinout Assignment V BB Figure 2. Logic Symbol Table 1. PIN DESCRIPTION PIN FUNCTION Table 2. TRUTH TABLE CLKa, CLKa ,CLKb CLKb ECL Differential Input Clocks CLK SEL Input Clock Q0:7, Q0:7 ECL Differential Outputs CLK SEL ECL Input Clock Select L CLKa Selected V Reference Voltage Output H CLKb Selected BB V , V Positive Supply CC CCO V Negative Supply EE NC No Connect Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor YES Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg PLCC28 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 212 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2