MC100LVEL14 3.3 VECL 1:5 Clock Distribution Chip Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if www.onsemi.com positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of 3.0 V to 20 3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the 1 distribution of a lower speed scan or test clock along with the high speed SOIC20 WB system clock. When LOW (or left open and pulled LOW by the input DW SUFFIX CASE 751D05 pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This MARKING DIAGRAM avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The 20 internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the 100LVEL14 negative edge of the clock input. AWLYYWWG The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. 1 BB V may also rebias AC coupled inputs. When used, decouple V and BB BB V via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 A = Assembly Location CC WL = Wafer Lot mA. When not used, V should be left open. BB YY = Year WW = Work Week Features G = Pb-Free Package 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input ORDERING INFORMATION ESD Protection: Human Body Model > 2 kV Device Package Shipping The 100 Series Contains Temperature Compensation MC100LVEL14DWG SOIC20 WB 38 Units / Tube (Pb-Free) PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V MC100LVEL14DWR2G 1000 Tape & Reel CC EE SOIC20 WB (Pb-Free) NECL Mode Operating Range: For information on tape and reel specifications, in- V = 0 V with V = 3.0 V to 3.8 V CC EE cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Internal Input Pulldown Resistors on CLK Brochure, BRD8011/D. Q Output will Default LOW with Inputs Open or at V EE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: Level 3 (Pb-Free) Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 303 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 10 MC100LVEL14/DMC100LVEL14 V EN V NC SCLK CLK CLK V SEL V CC CC BB EE Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION CLK, CLK ECL Diff Clock Inputs 1 0 SCLK ECL Scan Clock Input D EN ECL Sync Enable Q SEL ECL Clock Select Input Q Q ECL Diff Clock Outputs 0 4, 0 4 V Reference Voltage Output BB 1 2354 678 9 10 V Positive Supply CC Q0 Q1 Q2 Q3 Q4 Q0 Q1 Q2 Q3 Q4 V Negative Supply EE Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. NC No Connect Figure 1. Pinout (Top View) and Logic Diagram Table 2. FUNCTION TABLE CLK SCLK SEL EN Q L X L L L H X L L H X L H L L X H H L H X X X H L* *On next negative transition of CLK or SCLK X = Dont Care Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm SOIC20 WB 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2