MC100LVEP14DTG ON Semiconductor

MC100LVEP14 2.5V / 3.3V1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1to5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input MC100LVEP14 V EN V CLK1 CLK1 V CLK0 CLK0 CLK SEL V CC CC BB EE 20 19 18 17 16 15 14 13 12 11 10 D Q 1 2 3 4 56 78 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 20Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Table 2. FUNCTION TABLE Pin Type Function CLK0 CLK1 CLK SEL EN Q CLK0*, LVECL/LVPECL/ ECL/PECL/HSTL CLK Input L X L L L CLK0** HSTL H X L L H X L H L L CLK1*, LVECL/LVPECL/ ECL/PECL/HSTL CLK Input X H H L H CLK1** HSTL X X X H L* Q0:4, Q0:4 LVECL/LVPECL ECL/PECL Outputs *On next negative transition of CLK0 or CLK1 CLK SEL* LVECL/LVPECL ECL/PECL Active Clock Se- lect Input EN* LVECL/LVPECL ECL Sync Enable V LVECL/LVPECL Reference Voltage Output BB V Positive Supply CC V Negative Supply EE * Pins will default low when left open. **Pins will default to V /2 when left open. CC Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model > 2 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg TSSOP20 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 357 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.