5 VECL 1:4 Clock Distribution Chip MC10EL15, MC100EL15 Description The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The www.onsemi.com V pin, an internally generated voltage supply, is available to this device BB only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias BB BB AC coupled inputs. When used, decouple V and V via a 0.01 F BB CC 16 capacitor and limit current sourcing or sinking to 0.5 mA. When not used, 1 V should be left open. BB The EL15 features a multiplexed clock input to allow for the SOIC16 distribution of a lower speed scan or test clock along with the high D SUFFIX speed system clock. When LOW (or left open and pulled LOW by the CASE 751B05 input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will MARKING DIAGRAMS* only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The 10EL15G AWLYWW internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. 100EL15G The 100 series contains temperature compensation. AWLYWW Features 50 ps Output-to-Output Skew A = Assembly Location Synchronous Enable/Disable WL = Wafer Lot YY = Year Multiplexed Clock Input WW = Work Week PECL Mode Operating Range: G = Pb-Free Package V = 4.2 V to 5.7 V with V = 0 V CC EE *For additional marking information, refer to NECL Mode Operating Range: Application Note AND8002/D. V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN. These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Package Device Shipping 2500 / SOIC16 MC10EL15DR2G Tape & Reel (Pb-Free) MC100EL15DG SOIC16 48 Units/Tube (Pb-Free) 2500 / SOIC16 MC100EL15DR2G (Pb-Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 8 MC10EL15/DMC10EL15, MC100EL15 V EN SCLK CLK CLK V SEL V CC BB EE 16 15 14 13 12 11 10 9 1 0 D Q 1 2 3 4567 8 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Figure 1. Logic Diagram and Pinout Assignment Table 2. FUNCTION TABLE Table 1. PIN DESCRIPTION CLK* SCLK* SEL* EN* Q PIN FUNCTION CLK, CLK ECL Diff Clock Inputs L X L L L H X L L H SCLK ECL Scan Clock Input X L H L L EN ECL Sync Enable X H H L H SEL ECL Clock Select Input X X X H L(1) Q Q ECL Diff Clock Outputs 0 3, 0 3 *Pins will default low when left open. V Reference Voltage Output BB 1. On next negative transition of CLK or SCLK V Positive Supply CC V Negative Supply EE Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 1 kV Machine Model > 100 V Charged Device Model 2kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 103 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2