N08L63W2A 8Mb Ultra-Low Power Asynchronous CMOS SRAM 512K 16 bit Overview Features The N08L63W2A is an integrated memory device Single Wide Power Supply Range containing a 8 Mbit Static Random Access Memory 2.3 to 3.6 Volts organized as 524,288 words by 16 bits. The device Very low standby current is designed and fabricated using ON 4.0A at 3.0V (Typical) Semiconductors advanced CMOS technology to Very low operating current provide both high-speed performance and ultra-low 2.0mA at 3.0V and 1s(Typical) power. The device operates with two chip enable Very low Page Mode operating current (CE1 and CE2) controls and output enable (OE) to 1.0mA at 3.0V and 1s (Typical) allow for easy memory expansion. Byte controls Simple memory control (UB and LB) allow the upper and lower bytes to be Dual Chip Enables (CE1 and CE2) accessed independently and can also be used to Byte control for independent byte operation deselect the device. The N08L63W2A is optimal Output Enable (OE) for memory expansion for various applications where low-power is critical Low voltage data retention such as battery backup and hand-held devices. Vcc = 1.8V The device can operate over a very wide Very fast output enable access time o o temperature range of -40 C to +85 C and is 25ns OE access time available in JEDEC standard packages compatible Very fast Page Mode access time with other standard 512Kb x 16 SRAMs t = 25ns AAP Automatic power down to standby mode TTL compatible three-state output driver Product Family Standby Power Operating Operating Current (I ), Part Number Package Type Supply Speed Current (Icc), SB Temperature (Vcc) Typical Typical N08L63W2AB 48 - BGA 70ns 2.7V o o 2.3V - 3.6V 4 A2 mA 1MHz -40 C to +85 C 85ns 2.3V N08L63W2AB2 48 - BGA Green Pin Configuration Pin Descriptions 12 34 56 Pin Name Pin Function A A A A LB OE CE2 A -A 0 1 2 Address Inputs 0 18 I/O A A I/O WE Write Enable Input B UB CE1 8 3 4 0 CE1, CE2 Chip Enable Input I/O I/O A A I/O I/O C 9 10 5 6 1 2 OE Output Enable Input V I/O A A I/O V D SS 11 17 7 3 CC LB Lower Byte Enable Input V I/O A I/O V E NC CC 12 16 4 SS UB Upper Byte Enable Input I/O I/O A A I/O I/O F 14 13 14 15 5 6 I/O -I/O Data Inputs/Outputs 0 15 I/O A A I/O G NC WE V 15 12 13 7 Power CC A A A A A V H NC Ground 18 8 9 10 11 SS NC Not Connected 48 Pin BGA (top) 8 x 10 mm 2008 SCILLC. All rights reserved. Publication Order Number: July 2008 - Rev. 8 N08L63W2A/DWord Mux N08L63W2A Functional Block Diagram Word Address Address Inputs Decode A0 - A3 Logic Input/ Page 32K Page Address Output Address I/O0 - I/O7 x 16 word Inputs Mux Decode x 16 bit A4 - A18 and Logic RAM Array Buffers I/O8 - I/O15 CE1 CE2 Control WE Logic OE UB LB Functional Description 1 CE1 CE2 WE OE UB LB MODE POWER I/O - I/O 0 15 2 H X XX XX High Z Standby Standby 2 X L XX XX High Z Standby Standby 2 XX XX H H High Z Standby Standby 3 1 1 3 LHL Data In Active X L L Write 1 1 LH HL Data Out Active L L Read 1 1 LH H H High Z Active Active L L 1. When UB and LB are in select mode (low), I/O - I/O are affected as shown. When LB only is in the select mode only I/O - I/O 0 15 0 7 are affected as shown. When UB is in the select mode only I/O - I/O are affected as shown. 8 15 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. 1 Capacitance Item Symbol Test Condition Min Max Unit o Input Capacitance C 8pF V = 0V, f = 1 MHz, T = 25 C IN IN A o I/O Capacitance C 8pF V = 0V, f = 1 MHz, T = 25 C I/O IN A 1. These parameters are verified in device characterization and are not 100% tested Rev. 8 Page 2 of 10 www.onsemi.com