NB100LVEP224FAG ON Semiconductor

NB100LVEP224 2.5V/3.3V 2:1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable NB100LVEP224 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V 49 32 V CCO CCO 50 31 Q15 Q7 51 30 Q15 Q7 52 29 Q16 Q6 53 28 Q16 Q6 54 27 Q17 Q5 Q5 55 26 Q17 Q18 Q4 56 25 NB100LVEP224 Q4 Q18 57 24 Q3 Q19 58 23 Q3 Q19 59 22 Q20 Q2 60 21 Q2 Q20 61 20 Q1 62 19 Q21 Q1 63 18 Q21 V V CCO 64 17 CCO 12345 678 9 10 11 121314 1516 All V , V , and V pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally CC CCO EE conductive exposed pad on package bottom (see package case drawing) must be attached to a heatsinking conduit, capable of transfer- ring 1.2 Watts. This exposed pad is electrically connected to V internally. EE Figure 1. 64Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION Table 2. FUNCTION TABLE CLK0*, CLK0** ECL Differential Input Clock OE (1) CLK SEL Q0Q23 Q0Q23 CLK1*, CLK1** ECL Differential Input Clock CLK SEL* ECL Input CLK Select L L CLK0 CLK0 OE* ECL Output Enable L H CLK1 CLK1 Q0Q23, Q0Q23 ECL Differential Outputs H L L H V , V Positive Supply CC CCO H H L H V *** Negative Supply EE 1. The OE (Output Enable) signal is synchronized with the * Pins will default LOW when left open. falling edge of the LVPECL CLK signal. ** Pins will default HIGH when left open. ***The thermally conductive exposed pad on the bottom of the package is electrically connected to V internally. EE