NB3L8533 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer Description The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer wwwwww..onsemi.comonsemi.com designed explicitly for low output skew applications. The NB3L8533 features a multiplexed input which can be driven by MARKING either a differential or singleended input to allow for the distribution DIAGRAM of a lower speed clock along with the high speed system clock. The CLK SEL pin will select the differential clock inputs, CLK and CLK, when LOW (or left open and pulled LOW by the internal NB3L pulldown resistor). When CLK SEL is HIGH, the Differential 8533 PCLK and PCLK inputs are selected. ALYW TSSOP20 The common enable (CLK EN) is synchronous so that the outputs DT SUFFIX will only be enabled/disabled when they are already in the LOW state. CASE 948E This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous A = Assembly Location control. The internal flip flop is clocked on the falling edge of the input WL = Wafer Lot clock, therefore, all associated specification limits are referenced to YY = Year the negative edge of the clock input. WW = Work Week G = PbFree Package Features 650 MHz Maximum Clock Output Frequency + CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL CLK EN D Q PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL Q0 Four Differential LVPECL Clock Outputs Q0 CLK 1.5 ns Maximum Propagation Delay 0 CLK Q1 Operating Range: V = 2.375 V to 3.630 V CC Q1 + LVCMOS Compatible Control Inputs Q2 PCLK Q2 1 Selectable Differential Clock Inputs PCLK Q3 Synchronous Clock Enable + Q3 CLK SEL 30 ps Max. Skew Between Outputs 40C to +85C Ambient Operating Temperature Range TSSOP20 Package Figure 1. Simplified Logic Diagram of These are PbFree Devices NB3L8533 Applications Computing and Telecom ORDERING INFORMATION Routers, Servers and Switches See detailed ordering and shipping information on page 8 of this data sheet. Backplanes Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: December, 2014 Rev. 1 NB3L8533/DNB3L8533 V 1 20 Q0 EE CLK EN 2 19 Q0 CLK SEL 3 18 V CC 17 Q1 4 CLK 16 Q1 CLK 5 PCLK 15 6 Q2 PCLK 14 7 Q2 nc 13 8 V CC nc 12 Q3 9 V 11 Q3 CC 10 Figure 2. Pinout Diagram (Top View) Table 1. FUNCTIONS Inputs Outputs CLK EN CLK SEL Input Function Output Function Qx Qx 0 0 CLK input selected Disabled LOW HIGH 0 1 PCLK Inputs Selected Disabled LOW HIGH 1 0 CLK input selected Enabled CLK Invert of CLK 1 1 PCLK Inputs Selected Enabled PCLK Invert of PCLK 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. Table 2. PIN DESCRIPTION Open Pin Number Name I/O Default Description 1 VEE Power Negative (Ground) Power Supply pin must be externally connect- ed to power supply to guarantee proper operation. 2 CLK EN LVCMOS/LVTTL Pull-up Synchronized Clock Enable when HIGH. When LOW, outputs are Input disabled (Qx HIGH, Qx LOW) 3 CLK SEL LVCMOS/LVTTL Pull-down Clock Input Select (HIGH selects PCLK, LOW selects CLK input) Input 4 CLK Input Pull-down Noninverted Differential Clock Input. Float open when unused. 5 CLK Input Pull-up Inverted Differential Clock Input. Float open when unused. 6 PCLK Input Pull-down Noninverted Differential Clock Input. Float open when unused. 7 PCLK Input Pull-up Inverted Differential Clock Input. Float open when unused. 8 NC No Connect 9 NC No Connect 10 VCC Power Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. 11 Q3 LVPECL Output Complement Differential Output 12 Q3 LVPECL Output True Differential Output 13 VCC Power Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. 14 Q2 LVPECL Output Complement Differential Output 15 Q2 LVPECL Output True Differential Output 16 Q1 LVPECL Output Complement Differential Output 17 Q1 LVPECL Output True Differential Output 18 VCC Power Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. 19 Q0 LVPECL Output Complement Differential Output 20 Q0 LVPECL Output True Differential Output www.onsemi.com 2