3.3 V 12.288 MHz Audio Oversampling Clock Generator for USB Applications NB3N3010B www.onsemi.com Description The NB3N3010B is a precision, low noise clock multiplier that 8 generates an output frequency of 12.288 MHz. This is accomplished by using FrequencyLockedLoop (FLL) techniques where a 4 kHz 1 reference input is multiplied by 3072, or an 8 kHz input by 1536. The SOIC8 frequency multiplier is selected by the S0 pin. D SUFFIX The two LVCMOS output drivers are disabled to a logic Low with CASE 751 the ENABLEn pin set HIGH. The NB3N3010B operates from a single +3.3 V supply, and is available in the SOIC8 pin package. The operating temperature range is from 0C to +85C. MARKING DIAGRAM* The NB3N3010B device provides the optimum combination of low 8 cost, flexibility, and high performance. This makes it ideal for 3010B applications such as oversampling AtoD and D toA converters ALYW from a low reference frequency, such as a USB startofframe (SOF) pulse. 1 Features A = Assembly Location Accepts 8 kHz or 4 kHz Reference Input Derived from USB L = Wafer Lot Y = Year StartofFrame W = Work Week Generates 12.288 MHz FrequencyLocked to the Reference = PbFree Package Fully Integrated FrequencyLockLoop with Internal Loop Filter (Note: Microdot may be in either location) Low Skew Dual LVCMOS Outputs *For additional marking information, refer to Very Low Phase Noise Preserves Codec Noise Floor Application Note AND8002/D. Internal Voltage Regulator Supply Voltage Required: +3.3 V 5% ORDERING INFORMATION Temperature Range: 0C to +85C These Devices are PbFree, Halogen Free/BFR Free and are RoHS Device Package Shipping Compliant SOIC8 2500 / Tape NB3N3010BDR2G (PbFree) & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifica- tions Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2011 1 Publication Order Number: May, 2021 Rev. 1 NB3N3010B/DNB3N3010B VDD CFILT GND 8 5 4 CLK A +1.8 V Linear 6 Regulator REF CLK B Tolerant 3 Frequency Output Frequency Loop Filter 7 Generator Buffers Detector Divider 1 2 ENABLEn S0 Figure 1. NB3N3010B Simplified Diagram 1 ENABLEn 8 VDD S0 2 7 CLKB NB3N3010B 3 REF 6 CLKA GND 4 5 CFILT Figure 2. Pinout SOIC8 (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 ENABLEn LVTTL/ Low active Output Enable Defaults HIGH when left open Internal pullup resistor to LVCMOS Input V . DD 2 S0 LVTTL/ Frequency Select Input. See input frequency select Table 2 for details. Defaults HIGH LVCMOS Input when left open. Internal pullup resistor to V . DD 3 REF Input Reference Clock input 4 GND Power Supply Negative Supply Voltage Ground 0 V. This pin provides GND return path to the VDD supply. 5 CFILT Analog Connection for external filter capacitor for internal +1.8 V regulator see Figure 4. 6 CLKA LVCMOS Clock output, copy A (12.288 MHz) Output 7 CLKB LVCMOS Clock output, copy B (12.288 MHz) Output 8 VDD Power Supply Positive Supply Voltage, +3.3 V 5% www.onsemi.com 2