NB3V60113G 1.8 V Programmable OmniClock Generator with Single Ended (LVCMOS) and Differential (LVDS/HCSL) Outputs www.onsemi.com The NB3V60113G, which is a member of the OmniClock family, is a onetime programmable (OTP), low power PLLbased clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a single ended (LVCMOS) reference clock as input. It generates either WDFN8 three single ended (LVCMOS) outputs, or one single ended output and CASE 511AT one differential (LVDS/HCSL) output. The output signals can be modulated using the spread spectrum feature of the PLL MARKING DIAGRAM (programmable spread spectrum type, deviation and rate) for 1 applications demanding low electromagnetic interference (EMI). V0M Using the PLL bypass mode, it is possible to get a copy of the input clock on any or all of the outputs. The device can be powered down using the Power Down pin (PD ). It is possible to program the internal V0 = Specific Device Code M = Date Code input crystal load capacitance and the output drive current provided by = PbFree Device the device. The device also has automatic gain control (crystal power limiting) circuitry which avoids the device overdriving the external (Note: Microdot may be in either location) crystal. ORDERING INFORMATION Features See detailed ordering and shipping information on page 19 of Member of the OmniClock Family of Programmable Clock this data sheet. Generators Operating Power Supply: 1.8 V 0.1 V I/O Standards Inputs: LVCMOS, Fundamental Mode Crystal Power Saving mode through Power Down Pin Outputs: LVCMOS Programmable PLL Bypass Mode Outputs: LVDS and HCSL Programmable Output Inversion 3 Programmable Single Ended (LVCMOS) Outputs Programming and Evaluation Kit for Field from 8 kHz to 200 MHz Programming and Quick Evaluation 1 Programmable Differential Clock Output up to Temperature Range 40C to 85C 200 MHz Packaged in 8Pin WDFN Input Frequency Range These are PbFree Devices Crystal: 3 MHz to 50 MHz Reference Clock: 3 MHz to 200 MHz Typical Applications Configurable Spread Spectrum Frequency Modulation eBooks and Media Players Parameters (Type, Deviation, Rate) Smart Wearables, Portable Medical and Industrial Programmable Internal Crystal Load Capacitors Equipment Programmable Output Drive Current for Single Ended Set Top Boxes, Printers, Digital Cameras and Outputs Camcorders Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 2 NB3V60113G/DNB3V60113G BLOCK DIAGRAM PD VDD Crystal/Clock Control Output control Configuration Memory Frequency CMOS/ Output and SS CLK0 Diff Divider buffer PLL Block XIN/CLKIN Clock Buffer/ Crystal Phase Charge VCO CMOS / Crystal Output Oscillator and Detector Pump Diff CLK1 AGC Divider buffer XOUT Feedback Output CMOS CLK2 Divider Divider buffer PLL Bypass Mode GND Notes: 1. CLK0 and CLK1 can be configured to be one of LVDS or HCSL output, or two singleended LVCMOS outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. PD has internal pull down resistor. Figure 1. Simplified Block Diagram PIN FUNCTION DESCRIPTION XIN/CLKIN 1 8 CLK2 2 7 XOUT VDD NB3V60113G 3 6 CLK1 PD 4 5 GND CLK0 Figure 2. Pin Connections (Top View) WDFN8 www.onsemi.com 2