NB3V63143G 1.8 V Programmable OmniClock Generator with Single Ended (LVCMOS) and Differential (LVDS/HCSL) Outputs with Individual Output www.onsemi.com Enable and Individual VDDO The NB3V63143G, which is a member of the OmniClock family, is a onetime programmable (OTP), low power PLLbased clock 1 generator that supports any output frequency from 8 kHz to 200 MHz. QFN16 The device accepts fundamental mode parallel resonant crystal or a CASE 485AE single ended (LVCMOS) reference clock as input. It generates either three single ended (LVCMOS) outputs, or one single ended output and MARKING DIAGRAM one differential (LVDS/HCSL) output. The output signals can be modulated using the spread spectrum feature of the PLL 3V631 (programmable spread spectrum type, deviation and rate) for 43Gxx applications demanding low electromagnetic interference (EMI). ALYW Individual output enable pins OE 2:0 are available to enable/disable the outputs. Individual output voltage pins VDDO 2:0 are available 3V63143G = Specific Device Code to independently set the output voltage of each output. Up to four xx = Specific Program Code (Default different configurations can be written into the device memory. Two 00 for Unprogrammed Part) selection pins (SEL 1:0 ) allow the user to select the configuration to A = Assembly Location use. Using the PLL bypass mode, it is possible to get a copy of the L = Wafer Lot input clock on any or all of the outputs. The device can be powered Y = Year down using the Power Down pin (PD ). It is possible to program the W = Work Week = PbFree Package internal input crystal load capacitance and the output drive current (Note: Microdot may be in either location) provided by the device. The device also has automatic gain control (crystal power limiting) circuitry which avoids the device overdriving ORDERING INFORMATION the external crystal. See detailed ordering and shipping information on page 20 of this data sheet. Features Member of the OmniClock Family of Programmable Programmable Internal Crystal Load Capacitors Clock Generators Programmable Output Drive Current for Single Ended Operating Power Supply: 1.8 V 0.1 V Outputs I/O Standards Power Saving Mode through Power Down Pin Inputs: LVCMOS, Fundamental Mode Crystal Programmable PLL Bypass Mode Outputs: 1.8 V LVCMOS Programmable Output Inversion Outputs: LVDS and HCSL Programming and Evaluation Kit Available for Field 3 Programmable Single Ended (LVCMOS) Outputs Programming and Quick Evaluation from 8 kHz to 200 MHz Temperature Range 40C to 85C 1 Programmable Differential Clock Output up to Packaged in 16pin QFN 200 MHz These are PbFree Devices Input Frequency Range Typical Applications Crystal: 3 MHz to 50 MHz Reference Clock: 3 MHz to 200 MHz eBooks and Media Players Configurable Spread Spectrum Frequency Modulation Smart Wearables, Smart Phones, Portable Medical and Parameters (Type, Deviation, Rate) Industrial Equipment Individual Output Enable Pins Set Top Boxes, Printers, Digital Cameras and Camcorders Independent Output Voltage Pins Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 2 NB3V63143G/DNB3V63143G BLOCK DIAGRAM VDD PD SEL0 SEL1 Input Decoder Output control Configuration Crystal/Clock Control Memory VDDO0 Frequency CMOS/ Output and SS DIFF CLK0 Divider buffer PLL Block XIN/ CLKIN Reference OE0 Clock Buffer/ Clock Crystal Phase Charge VDDO1 VCO Oscillator And Detector Pump Crystal CMOS/ AGC XOUT Output CLK1 DIFF Divider buffer Feedback OE1 Divider VDDO2 Output CMOS CLK2 Divider buffer PLL Bypass Mode OE2 GND GNDO Notes: 1. CLK0 and CLK1 can be configured to be one LVDS or HCSL output, or two single ended LVCMOS outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. OE 2:0 , SEL 1:0 have internal pull up resistors. PD has internal pull down resistor. Figure 1. Simplified Block Diagram PIN FUNCTION DESCRIPTION 16 15 14 13 NB3V63143G XIN/CLKIN 1 12 VDD XOUT 2 11 VDDO1 GNDO (EPAD) PD 3 10 CLK1 GND 4 9 CLK0 5 6 7 8 Figure 2. Pin Connections (Top View) QFN16 (with EPAD) www.onsemi.com 2 OE0 SEL0 OE1 SEL1 OE2 VDDO2 VDDO0 CLK2