2.5 V/3.3 V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer NB4L6254 www.onsemi.com Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout buffers. It employs a fully differential architecture with bipolar technology, LQFP32 offers superior digital signal characteristics, has very low clock output FA SUFFIX skew and supports clock frequencies from DC up to 3.0 GHz. CASE 561AB The NB4L6254 is designed for the most demanding, skew critical differential clock distribution systems. Typical applications for the MARKING DIAGRAM* NB4L6254 are clock distribution, switching and data loopback systems of high performance computer, networking and NB4L telecommunication systems, as well as onboard clocking of OC3, 6254 OC 12 and OC 48 communication systems. In addition, the AWLYYWWG NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL fanout buffer. The NB4L6254 can be operated from a single 3.3 V or 2.5 V power A = Assembly Location supply. WL = Wafer Lot YY = Year Features WW = Work Week Maximum Clock Input Frequency, 3 GHz G = PbFree Package (Note: Microdot may be in either location) Maximum Input Data Rate, 3 Gb/s *For additional marking information, refer to Differential LVPECL Inputs and Outputs Application Note AND8002/D. Low Output Skew: 50 ps Maximum OutputtoOutput Skew Synchronous Output Enable Eliminating Output Runt Pulse V CC Generation and Metastability Bank A QA0 Operating Range: Single 3.3 V or 2.5 V Supply CLK0 0 QA0 CLK0 V = 2.375 V to 3.465 V CC QA1 QA1 LVCMOS Compatible Control Inputs 1 QA2 QA2 Packaged in LQFP32 V CC Fully Differential Architecture Bank B QB0 CLK1 40C to 85C Ambient Operating Temperature 0 QB0 CLK1 QB1 These are PbFree Devices* QB1 1 QB2 QB2 SEL0 SEL1 OEA SYNC OEB Figure 1. Functional Block Diagram *For additional information on our PbFree strategy and soldering details, please ORDERING INFORMATION download the ON Semiconductor Soldering and Mounting Techniques See detailed ordering and shipping information in the package Reference Manual, SOLDERRM/D. dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: June, 2021 Rev. 4 NB4L6254/DNB4L6254 QA0 QA0 V QA1 QA1 V QA2 QA2 CC CC 32 31 30 29 28 27 26 25 V 24 CC 1 V CC GND 23 GND 2 SEL1 OEA 22 3 CLK1 21 CLK0 4 NB4L6254 CLK1 20 5 CLK0 SEL0 OEB 6 19 GND 7 GND 18 V V CC CC 17 8 9 10 11 12 13 14 15 16 QB0 QB0 V QB1 QB1 V QB2 QB2 CC CC Figure 2. 32Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description CLK0, CLK0 LVPECL Input Differential reference clock signal input 0. CLK1, CLK1 LVPECL Input Differential reference clock signal input 1. OEAb, OEB LVCMOS Input Output Enable SEL0, SEL1 LVCMOS Input Clock Switch Select QA 02 , QA 02 LVPECL Output Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 resistor to V 2.0 V. CC QB 02 , QB 02 GND Power Supply Negative Supply Voltage V Power Supply Positive supply voltage. All V pins must be connected to the positive power supply CC CC for correct DC and AC operation. Table 2. FUNCTION TABLE Control Default 0 1 OEA 0 QA 02 , QA 02 are active. Deassertion of QA 02 = L, QA 02 = H (outputs disabled). Assertion of OEA can be asynchronous to the reference OE can be asynchronous to the reference clock without clock without generation of output runt pulses generation of output runt pulses OEB 0 QB 02 , QB 02 are active. Deassertion of QB 02 = L, QB 02 = H (outputs disabled). Assertion of OEB can be asynchronous to the reference OE can be asynchronous to the reference clock without clock without generation of output runt pulses generation of output runt pulses SEL0, 00 Refer to Table 3 Refer to Table 3 SEL1 www.onsemi.com 2