NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator Description NB4N11M Q0 1 8 V CC Q0 2 7 D 6 D Q1 3 Q1 4 5 V EE Figure 2. Pinout (Top View) and Logic Diagram Table 1. Pin Description Pin Name I/O Description 1 Q0 CML Output Noninverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at TT TT powerup. 2 Q0 CML Output Inverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at powerup. TT TT 3 Q1 CML Output Noninverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at TT TT powerup. 4 Q1 CML Output Inverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at powerup. TT TT 5 V Negative supply voltage. EE 6 D LVPECL, CML, HSTL, Inverted differential input. LVCMOS, LVDS, LVTTL Input 7 D LVPECL, CML, HSTL, Noninverted differential input. LVCMOS, LVDS, LVTTL Input 8 V Positive supply voltage. CC