1.8 V/2.5 V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator MultiLevel Inputs w/ Internal Termination www.onsemi.com NB7V72M MARKING Description DIAGRAM* The NB7V72M is a high bandwidth, low voltage, fully differential 16 2 x 2 crosspoint switch with CML outputs. The NB7V72M design is 1 optimized for low skew and minimal jitter as it produces two identical NB7V copies of Clock or Data operating up to 5 GHz or 6.5 Gb/s, 72M 1 respectively. As such, the NB7V72M is ideal for SONET, GigE, Fiber ALYW QFN16 Channel, Backplane and other clock/data distribution applications. MN SUFFIX The differential IN/IN inputs incorporate internal 50 termination CASE 485G resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 10). The 16 mA differential CML outputs provide matching A = Assembly Location internal 50 terminations and produce 400 mV output swings when L = Wafer Lot externally terminated with a 50 resistor to V (see Figure 11). The CC Y = Year NB7V72M is the 1.8 V/2.5 V CML version of the NB7L72M and is W = Work Week offered in a low profile 3x3 mm 16pin QFN package. Application = PbFree Package (Note: Microdot may be in either location) notes, models, and support documentation are available at www.onsemi.com. *For additional marking information, refer to The NB7V72M is a member of the GigaComm family of high Application Note AND8002/D. performance clock products. Features + Maximum Input Data Rate > 6.5 Gb/s SEL0 Data Dependent Jitter < 15 ps pkpk Maximum Input Clock Frequency > 5 GHz IN0 Random Clock Jitter < 0.8 ps RMS, Max Q0 VT0 150 ps Typical Propagation Delay 0 30ps Typical Rise and Fall Times IN0 Q0 1 Differential CML Outputs, 400 mV peaktopeak, typical Operating Range: V = 1.71 V to 2.625 V with GND = 0 V CC Internal 50 Input Termination Resistors QFN16 Package, 3mm x 3mm 40C to +85C Ambient Operating Temperature These are PbFree Devices Q1 0 IN1 VT1 Q1 1 + IN1 SEL1 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: May, 2021 Rev. 2 NB7V72M/DNB7V72M Exposed Pad (EP) VT0 SEL0 GND VCC Table 1. INPUT/OUTPUT SELECT TRUTH TABLE 16 15 14 13 SEL0* SEL1* Q0 Q1 L L IN0 IN0 IN0 1 12 Q0 L H IN0 IN1 IN0 2 11 Q0 H L IN1 IN0 NB7V72M H H IN1 IN1 IN1 Q1 3 10 *Defaults HIGH when left open IN1 Q1 4 9 56 7 8 VT1 SEL1 GND VCC Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IN0 LVPECL, CML, Noninverted Differential Input. (Note 1) LVDS Input 2 IN0 LVPECL, CML, Inverted Differential Input. (Note 1) LVDS Input 3 IN1 LVPECL, CML, Inverted Differential Input. (Note 1) LVDS Input 4 IN1 LVPECL, CML, Noninverted Differential Input. (Note 1) LVDS Input 5 VT1 Internal 50 Termination Pin for IN1 and IN1 6 SEL1 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth Table pin defaults HIGH when left open. 7 GND Negative Supply Voltage 8 VCC Positive Supply Voltage 9 Q1 CML Output Noninverted Differential Output. (Note 1) 10 Q1 CML Output Inverted Differential Output. (Note 1) 11 Q0 CML Output Inverted Differential Output. (Note 1) 12 Q0 CML Output Noninverted Differential Output. (Note 1) 13 VCC Positive Supply Voltage 14 GND Negative Supply Voltage 15 SEL0 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth Table pin defaults HIGH when left open. 16 VT0 Internal 50 Termination Pin for IN0 and IN0 EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2