Dual-Channel/Multi-Phase Controller for DrMOS NCP81232 The NCP81232, a dualchannel/multiphase synchronous buck controller, provides power management solutions for various applications supported by DrMOS. It has 8 programmable www.onsemi.com powerstage configurations, differential voltage and current sense, flexible power sequence programming, and comprehensive protections. MARKING Features DIAGRAM Vin = 4.5~20 V with Input Feedforward 1 Integrated 5.35 V LDO 1 40 Vout = 0.6 V ~ 5.3 V NCP81232 QFN40 AWLYYWW Fsw = 200k ~ 1.2 MHz CASE 485CR PWM Output Compatible to 3.3 V and 5 V DrMOS Flexible 8 Combinations of Power Stage Configurations (1~2 Output A = Assembly Location Rails, 1~4 Phases) WL = Wafer Lot DDR Power Mode Option YY = Year Interleaved Operation WW = Work Week = PbFree Package Differential Output Voltage Sense (Note: Microdot may be in either location) Differential Current Sense Compatible for both Inductor DCR Sense and DrMOS Iout 2 Enables with Programmable Input UVLO ORDERING INFORMATION Programmable DrMOS Power Ready Detection (DRVON) Device Package Shipping 2 Power Good Indicators Comprehensive Fault Indicator NCP81232MNTXG QFN40 5000 / (PbFree) Tape & Reel Externally Programmable Soft Start and Delay Time Programmable Hiccup Over Current Protection For information on tape and reel specifications, including part orientation and tape sizes, please Hiccup Under Voltage Protection refer to our Tape and Reel Packaging Specification Recoverable Over Voltage Protection Brochure, BRD8011/D. Hiccup Over Temperature Protection Thermal Shutdown Protection QFN40, 5x5 mm, 0.4 mm Pitch Package This is a PbFree Device Typical Applications Telecom Applications Server and Storage System Multiple Rail Systems DDR Applications Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: September, 2020 Rev. 3 NCP81232/DNCP81232 40 39 38 37 36 35 34 33 32 31 1 VIN ISP1 30 2 EN1 ISN1 29 3 EN2 ISP2 28 4 DRVON ISN2 27 5 PGOOD1 PWM2 26 GND 41 6 PGOOD2 PWM3 25 7 FAULT ISP3 24 8 DLY 1 ISN3 23 DLY 2 9 ISP4 22 / DDR 10 SS ISN4 21 11 12 13 14 15 16 17 18 19 20 Figure 1. Pin Configuration PIN DESCRIPTION Pin Name Type Description 1 VIN Power Input Power Supply Input. Power supply input pin of the device, which is connected to the integrated 5V LDO. 4.7 F or more ceramic capacitors must bypass this input to power ground. The capacitors should be placed as close as possible to this pin. 2 EN1 Analog Input Enable 1. Logic high enables channel 1 and logic low disables channel 1. Input supply UVLO can be programmed at this pin for channel 1. 3 EN2 Analog Input Enable 2. Logic high enables channel 2 and logic low disables channel 2. Input supply UVLO can be programmed at this pin for channel 2. 4 DRVON Logic Input Driver On. Logic high input means drivers power is ready. 5 PGOOD1 Logic Output Power GOOD 1. Opendrain output. Provides a logic high valid power good output signal, indicating the regulators output is in regulation window of channel 1. 6 PGOOD2 Logic Output Power GOOD 2. Opendrain output. Provides a logic high valid power good output signal, indicating the regulators output is in regulation window of channel 2. 7 FAULT Logic Output Fault. Digital output to indicate fault mode. 8 DLY1 Analog Input Delay 1. A resistor from this pin to GND programs delay time of soft start for channel 1. 9 DLY2 Analog Input Delay 2 / DDR. A resistor from this pin to GND programs delay time of soft start for channel 2. Short to GND to have DDR operation mode. /DDR 10 SS Analog Input Soft Start Time. A resistor from this pin to ground programs soft start time for both channels. 11 FSET Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency. 12 CNFG Analog Input Configuration. A resistor from this pin to ground programs configuration of power stages. 13 ILIMT2 Analog Input Limit of Current 2. Voltage at this pin sets overcurrent threshold for channel 2. www.onsemi.com 2 FSET VCC5V CNFG VREF ILMT2 ILMT1 OTP2 OTP1 /REFIN COMP2 COMP1 FB2 FB1 DIFFOUT2 DIFFOUT1 VSN2 VSN1 VSP2 VSP1 PWM4 PWM1