P1P3800AG12CRTWG ON Semiconductor

P1P3800A Phase Synchronizing Clock Generator Product Description P1P3800A is a Phase Synchronizing clock generator that generates four outputs from an input clock. Output frequency will be a divide by P1P3800A Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 S2 I Output clock select. Refer Output Clock selection table. Has NO default state 2 S1 I Output clock select. Refer Output Clock selection table. Has NO default state. 3 CLKIN I External Reference Clock Input 4 S3 I Output clock select. Refer Output Clock selection table. Has NO default state. 5 GND P Ground to entire chip 6 S4 I Output clock select. Refer Output Clock selection table. Has NO default state. 7 CLKOUT3 O Buffered clock output. Refer CLKOUT Diagram 8 CLKOUT4 O Buffered clock output. Refer CLKOUT Diagram 9 PD# I Power Down. Powers down the entire chip when pulled LOW. CLKOUT [1:4] will be LOW when power down is enabled. Has NO default state. 10 CLKOUT2 O Buffered clock output. Refer CLKOUT Diagram 11 V P Supply Voltage DD 12 CLKOUT1 O Buffered clock output. Refer CLKOUT Diagram Table 2. OUTPUT CLOCK SELECTION TABLE S4 S3 S2 S1 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 0 0 0 0 Low Low Low Low 0 0 0 1 CLK# CLK# CLK# CLK 0 0 1 0 CLK# CLK# CLK CLK# 0 0 1 1 CLK# CLK# CLK CLK 0 1 0 0 CLK# CLK CLK# CLK# 0 1 0 1 CLK# CLK CLK# CLK 0 1 1 0 CLK# CLK CLK CLK# 0 1 1 1 CLK# CLK CLK CLK 1 0 0 0 CLK CLK# CLK# CLK# 1 0 0 1 CLK CLK# CLK# CLK 1 0 1 0 CLK CLK# CLK CLK# 1 0 1 1 CLK CLK# CLK CLK 1 1 0 0 CLK CLK CLK# CLK# 1 1 0 1 CLK CLK CLK# CLK 1 1 1 0 CLK CLK CLK CLK# 1 1 1 1 CLK CLK CLK CLK