Product Specification PE4304 75 RF Digital Attenuator 6-bit, 31.5 dB, DC 2.0 GHz Product Description Features The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step 75 impedance Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5 Attenuation: 0.5 dB steps to 31.5 dB dB steps. The PE4304 provides both a parallel (latched or direct mode) and serial CMOS control interface, operates on a Low distortion for CATV and multi-carrier single 3-volt supply and maintains high attenuation accuracy applications over frequency and temperature. It also has a unique control Flexible parallel and serial programming interface that allows the user to select an initial attenuation interfaces state at power-up. The PE4304 exhibits very low insertion loss Unique power-up state selection and low power consumption. This functionality is delivered in a Positive CMOS control logic 4x4 mm QFN footprint. High attenuation accuracy and linearity over temperature and frequency The PE4304 is manufactured on Peregrines UltraCMOS Very low power consumption process, a patented variation of silicon-on-insulator (SOI) Single-supply operation technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional Packaged in a 20 lead 4x4 mm QFN CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 4x4 mm 20-Lead QFN Switched Attenuator Array RF Input RF Output 6 Parallel Control Control Logic Interface 3 Serial Control 2 Power-Up Control Table 1. Electrical Specifications +25 C, V = 3.0 V, Z = 75 DD o Parameter Test Conditions Frequency Minimum Typical Maximum Units Operation Frequency DC 2000 MHz 2 Insertion Loss DC 1.2 GHz - 1.4 1.8 dB Any Bit or Bit (0.15 + 4% of attenuation Attenuation Accuracy DC 1.2 GHz - - dB Combination setting) 3,4 1 dB Compression 1 MHz 1.2 GHz 30 34 - dBm Two-tone inputs up to 1,2,4 Input IP3 1 MHz 1.2 GHz - 52 - dBm +18 dBm Return Loss DC 1.2 GHz 10 13 - dB 50% control to 0.5 dB Switching Speed - - 1 s of final value Notes: 1. Device Linearity will begin to degrade below 1Mhz 2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency. 3. Note Absolute Maximum in Table 3. 4. Measured in a 50 system. Document No. 70-0066-04 www.psemi.com 2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE4304 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V Power supply voltage -0.3 4.0 V DD V + DD V Voltage on any input -0.3 V I 0.3 C16 1 15 C8 T Storage temperature range -65 150 C ST RF1 2 14 RF2 P Input power (50) +30 dBm 20-lead QFN IN 3 4x4mm Data 13 P/S ESD voltage (Human Body V 500 V ESD Exposed Solder Pad Model) 4 Clock 12 Vss/GND Table 4. Operating Ranges 5 11 LE GND Parameter Min Typ Max Units V Power Supply DD 2.7 3.0 3.3 V Voltage I Power Supply DD 100 A Current Table 2. Pin Descriptions Digital Input High 0.7xV V DD Pin Pin Digital Input Low 0.3xV V DD Description No. Name 1 C16 Attenuation control bit, 16dB (Note 4). Digital Input Leakage 1 A 2 RF1 RF port (Note 1). Input Power +24 dBm 3 Data Serial interface data input (Note 4). Temperature range -40 85 C 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). Exposed Solder Pad Connection 6 V Power supply pin. DD The exposed solder pad on the bottom of the 7 PUP1 Power-up selection bit, MSB. package must be grounded for proper device 8 PUP2 Power-up selection bit, LSB. operation. 9 V Power supply pin. DD Electrostatic Discharge (ESD) Precautions 10 GND Ground connection. When handling this UltraCMOS device, observe 11 GND Ground connection. the same precautions that you would use with other 12 V /GND Negative supply voltage or GND ss ESD-sensitive devices. Although this device connection(Note 3) contains circuitry to protect it from damage due to 13 P/S Parallel/Serial mode select. ESD, precautions should be taken to avoid 14 RF2 RF port (Note 1). exceeding the rate specified in Table 3. 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. Latch-Up Avoidance 17 C2 Attenuation control bit, 2 dB. Unlike conventional CMOS devices, UltraCMOS 18 GND Ground connection. devices are immune to latch-up. 19 C1 Attenuation control bit, 1 dB. Switching Frequency 20 C0.5 Attenuation control bit, 0.5 dB. The PE4304 has a maximum 25 kHz switching rate. Paddle GND Ground for proper operation Note 1: Both RF ports must be DC blocked with an external series Resistor on Pin 1 & 3 capacitor or held at 0 V . DC A 10 k resistor on the inputs to Pin 1 & 3 (see 2: Latch Enable (LE) has an internal 100 k resistor to V DD. 3: Connect pin 12 to GND to enable internal negative voltage Figure 5) will eliminate package resonance between generator. Connect pin 12 to V (-V ) to bypass and SS DD the RF input pin and the two digital inputs. Specified disable internal negative voltage generator. attenuation error versus frequency performance is 4. Place a 10 k resistor in series, as close to pin as possible. dependent upon this condition. 2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: