Product Specification PE64906 UltraCMOS Digitally Tunable Capacitor (DTC) 100 - 3000 MHz Product Description Features PE64906 is a DuNE technology-enhanced digitally tunable capacitor (DTC) based on Peregrines UltraCMOS 3-wire (SPI compatible) serial interface technology. This highly versatile product supports a wide with built-in bias voltage generation and variety of tuning circuit topologies with emphasis on ESD protection impedance matching and aperture tuning applications. DuNE technology enhanced 5-bit 32-state digitally tunable capacitor PE64906 offers high RF power handling and ruggedness while meeting challenging harmonic and linearity Shunt configuration C = 0.9 pF to 4.6 pF requirements enabled by Peregrines HaRP technology. (5.1:1 tuning ratio) in discrete 119 fF The device is controlled through the widely supported 3-wire steps (SPI compatible) interface. All decoding and biasing is High RF power handling (30 V RF) and pk integrated on-chip and no external bypassing or filtering linearity components are required. Wide power supply range (2.3V to 4.8V) DuNE devices feature ease of use while delivering superior and low current consumption RF performance in the form of tuning accuracy, monotonicity, (typ. 140 A at 2.75V) tuning ratio, power handling, size, and quality factor. With High ESD tolerance of 2 kV HBM on all built-in bias voltage generation and ESD protection, DTC pins products provide a monolithically integrated tuning solution Applications include: for demanding RF applications. Tunable antennas Tunable matching networks Tunable filter networks Phase shifters Figure 1. Functional Diagram Figure 2. Package Type 10-lead 2 x 2 x 0.55 mm QFN RF- RF+ ESD ESD CMOS Control Serial Interface Driver and ESD DOC-02169 Document No. DOC-82123-3 www.psemi.com 2017 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE64906 Product Specification Table 1. Electrical Specifications 25 C, V = 2.75V (In shunt configuration, RF- connected to GND) DD Parameter Condition Min Typ Max Unit Operating frequency 100 3000 MHz Minimum capacitance (C ) State = 00000, 100 MHz 0.81 0.9 0.99 pF min Maximum capacitance State = 11111, 100 MHz 3.68 4.6 5.52 pF (C ) max Tuning ratio C /C , 100 MHz 5.1:1 max min Step size 5 bits (32 states), 100 MHz 0.119 pF 698960 MHz, with L removed 40 1 S Quality factor at C min 17102170 MHz, with L removed 40 S 698960 MHz, with L removed 29 S 1 Quality factor at C max 17102170 MHz, with L removed 13 S State 00000 7.9 Self resonant frequency GHz State 11111 2.8 2fo, 3fo: 698915 MHz P = +34 dBm, 50 36 dBm IN 2 Harmonics 2fo, 3fo: 17101910 MHz P = +32 dBm, 50 36 dBm IN Bands I,II,V/VIII, +20 dBm CW TX freq, IMD3 105 dBm 15 dBm CW 2TX-RX freq, 50 Third order intercept point Shunt configuration derived from IMD3 spec 65 dBm (IP3) IP3 = (2P + P IMD3) / 2 TX block 3,4 Switching time State change to 10/90% delta capacitance between any two states 12 s 3 Start-up time Time from V within specification to all performances within specification 70 s DD 3,4 Wake-up time State change from Standby mode to RF state to all performances within specification 70 s Notes: 1. Q for a shunt DTC based on a series RLC equivalent circuit Q = X / R = (X - X ) / R, where X = X + X , X = 2*pi*f*L, X = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L C L L C L C S 2. In shunt between 50 ports. Pulsed RF input with 4620 S period, 50% duty cycle, measured per 3GPP TS 45.005 3. DC path to ground at RF must be provided to achieve specified performance 4. State change activated on falling edge of SEN following data word 2017 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-82123-3 UltraCMOS RFIC Solutions Page 2 of 11