DATASHEET SYSTEM PERIPHERAL CLOCK SOURCE ICS650-21 Description Features The ICS650-21 is a low cost, low-jitter, high-performance Packaged in 20-pin SSOP (QSOP) clock synthesizer for system peripheral applications. Using Pb (lead) free package, RoHS compliant analog/digital Phase Locked Loop (PLL) techniques, the Lower jitter version of ICS650-01 device accepts a parallel resonant 25 MHz crystal input to produce up to eight output clocks. The device provides Operating voltage of 3.3 V or 5 V clocks for PCI, SCSI, Fast Ethernet, Ethernet, USB, and Zero ppm synthesis error in all clocks AC97. The user can select one of three USB frequencies Inexpensive 25 MHz crystal or clock input and also one of two AC97 audio frequencies. The OE pin puts all outputs into a high-impedance state for board level Provides Ethernet and Fast Ethernet clocks testing. All frequencies are generated with less than one Provides SCSI clocks ppm error, meeting the demands of SCSI and Ethernet Provides PCI clocks clocking. Selectable AC97 audio clock Selectable USB clock OE pin tri-states the outputs for testing Selectable frequencies on three clocks Duty cycle of 45/55 for Processor clock and Audio clock Advanced, low-power CMOS process Industrial temperature range available Block Diagram VDD 3 2 3 Processor PSEL1:0 Clocks ASEL Audio Clock Clock USEL Synthesis Circuitry USB Clock 20 MHz X1/ICLK Crystal 25 MHz 25 MHz Oscillator Crystal or Clock X2 2 Optional crystal OE (all outputs) GND capacitors IDT / ICS SYSTEM PERIPHERAL CLOCK SOURCE 1 ICS650-21 REV J 051310ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCKSYNTHESIZER Pin Assignment Processor Clock (MHz) 1 20 PSEL1 USEL PSEL1 PSEL0 PCLK1 PCLK2, 3 X2 2 19 PSEL0 00 25 50 3 18 PCLK2 X1/ICLK 0M TEST MODE VDD 4 17 PCLK3 01 TEST MODE VDD 5 16 VDD M0 40 80 GND 6 15 ASEL UCLK 7 14 GND M M 33.3333 66.6667 8 13 20M OFF/14.318M M1 20 40 ACLK 9 12 PCLK1 1 0 20 33.3333 25M 10 11 OE 1 M 20 66.6667 1 1 50 100 20-pin (150 mil) SSOP Audio Clock (MHz) USB Clock (MHz) ASEL ACLK USEL UCLK 0 49.152 012 M 24.576 M24 1 14.318 148 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 USEL Input UCLK select pin. Determines frequency of USB clock per table above. 2 X2 XO Crystal connection. Connect to parallel mode 25 MHz crystal. Leave open for clock. 3 X1/ICLK XI Crystal connection. Connect to parallel mode 25 MHz crystal or clock. 4 VDD Power Connect to VDD. Must be same value as other VDD. Decouple with pin 6. 5 VDD Power Connect to VDD. Must be same value as other VDD. 6 GND Power Connect to ground. 7 UCLK Output USB clock output per table above. 8 20M Output Fixed 20 MHz output for Ethernet. 9 ACLK Output AC97 audio clock output per table above. 10 25M Output Fixed 25 MHz reference output for Fast Ethernet. 11 OE Input Output enable. Tri-states all outputs when low. 12 PCLK1 Output PCLK output number 1 per table above. IDT / ICS SYSTEM PERIPHERAL CLOCK SOURCE 2 ICS650-21 REV J 051310