74LVC16373APVG Renesas

IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVC16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: Typical tSK(o) (Output Skew) < 250ps The LVC16373A 16-bit transparent D-type latch is built using advanced ESD > 2000V per MIL-STD-883, Method 3015 > 200V using dual metal CMOS technology. This high-speed, low-power latch is ideal machine model (C = 200pF, R = 0) for temporary storage of data. The LVC16373A can be used for implement- VCC = 3.3V 0.3V, Normal Range ing memory address latches, I/O ports, and bus drivers. The Output Enable VCC = 2.7V to 3.6V, Extended Range and Latch Enable controls are organized to operate each device as two 8- CMOS power levels (0.4 W typ. static) bit latches or one 16-bit latch. Flow-through organization of signal pins All inputs, outputs, and I/O are 5V tolerant simplifies layout. All inputs are designed with hysteresis for improved noise Supports hot insertion margin. Available in SSOP and TSSOP packages All pins of the LVC16373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ DRIVE FEATURES: 5V supply system. High Output Drivers: 24mA The LVC16373A has been designed with a 24mA output driver. This Reduced system switching noise driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: 5V and 3.3V mixed voltage systems Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 24 1 1OE 2OE 25 48 2LE 1LE 47 36 D D 1D1 2D1 13 2 Q Q 1Q1 C 2Q1 C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JULY 2015 1 2015 Integrated Device Technology, Inc. DSC-4624/6IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 mA 1LE 1 48 1OE IIK Continuous Clamp Current, 50 mA 2 1D1 1Q1 47 IOK VI < 0 or VO < 0 1D2 ICC Continuous Current through each 100 mA 1Q2 3 46 ISS VCC or GND GND 4 GND 45 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 5 1D3 44 1Q3 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 6 1D4 1Q4 43 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VCC VCC 7 42 1D5 8 1Q5 41 1D6 9 40 1Q6 GND 10 CAPACITANCE (TA = +25C, F = 1.0MHz) GND 39 (1) Symbol Parameter Conditions Typ. Max. Unit 11 1D7 38 1Q7 CIN Input Capacitance VIN = 0V 4.5 6 pF 1D8 12 1Q8 37 COUT Output Capacitance VOUT = 0V 6.5 8 pF 13 2D1 2Q1 36 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 2D2 14 2Q2 35 1. As applicable to the device type. GND GND 15 34 16 33 2D3 2Q3 17 32 2D4 PIN DESCRIPTION 2Q4 18 31 Pin Names Description VCC VCC xDx Data Inputs 19 30 2D5 2Q5 xLE Latch Enable Input (Active HIGH) 20 29 2D6 2Q6 xOE Output Enable Inputs (Active LOW) x Q x 3-State Outputs 21 GND 28 GND 22 27 2D7 2Q7 23 2D8 26 2Q8 (1) FUNCTION TABLE 24 2LE 2OE 25 Inputs Outputs xDx xLE xOE xQx SSOP/ TSSOP TOP VIEW HH L H LH L L (2) XL L Q XX H Z NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2