74LVC16374APAG Renesas

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVC16374A EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16374A 16-bit edge-triggered D-type flip-flop is built using Typical tSK(o) (Output Skew) < 250ps advanced dual metal CMOS technology. This high-speed, low-power ESD > 2000V per MIL-STD-883, Method 3015 > 200V using register is ideal for use as a buffer register for data synchronization and machine model (C = 200pF, R = 0) storage. The Output Enable (OE) and clock (CLK) controls are organized VCC = 3.3V 0.3V, Normal Range to operate this device as two 8-bit registers or one 16-bit register with VCC = 2.7V to 3.6V, Extended Range common clock. Flow-through organization of signal pins simplifies layout. CMOS power levels (0.4 W typ. static) All inputs are designed with hysteresis for improved noise margin. All inputs, outputs, and I/O are 5V tolerant All pins of the LVC16374A can be driven from either 3.3V or 5V devices. Supports hot insertion This feature allows the use of this device as a translator in a mixed 3.3V/ Available in TSSOP package 5V supply system. DRIVE FEATURES: The LVC16374A has been designed with a 24mA output driver. This High Output Drivers: 24mA driver is capable of driving a moderate to heavy load while maintaining Reduced system switching noise speed performance. APPLICATIONS: 5V and 3.3V mixed voltage systems Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 48 25 1CLK 2CLK 47 36 D D 1D1 2D1 2 13 C 2Q1 C 1Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 2015 1 2015 Integrated Device Technology, Inc. DSC-4752/6IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V 1CLK 1OE 1 48 TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 mA 2 1D1 47 1Q1 IIK Continuous Clamp Current, 50 mA 1D2 1Q2 3 46 IOK VI < 0 or VO < 0 ICC Continuous Current through each 100 mA GND 4 GND 45 ISS VCC or GND 5 1D3 1Q3 44 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 6 1D4 1Q4 43 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational VCC VCC 7 42 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 8 1D5 1Q5 41 1D6 1Q6 9 40 CAPACITANCE (TA = +25C, F = 1.0MHz) GND 10 GND 39 (1) Symbol Parameter Conditions Typ. Max. Unit 11 1D7 38 1Q7 CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF 12 1D8 1Q8 37 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 2D1 13 2Q1 36 NOTE: 1. As applicable to the device type. 2D2 14 2Q2 35 GND GND 15 34 PIN DESCRIPTION 16 33 2D3 2Q3 Pin Names Description 17 32 2D4 2Q4 xDx Data Inputs 18 31 VCC VCC xCLK Clock Inputs xOE 3-State Output Enable Inputs (Active LOW) 19 30 2D5 2Q5 x Q x 3-State Outputs 20 29 2D6 2Q6 21 GND 28 GND (1) 22 FUNCTION TABLE(EACH FLIP-FLOP) 27 2D7 2Q7 Inputs Outputs 23 2D8 26 2Q8 xDx xCLK xOE xQx 24 2CLK 2OE 25 XL H Z XH H Z TSSOP L LL TOP VIEW H LH (2) LH L Q (2) HL L Q NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2