SINGLE CHANNEL T1/E1/J1 IDT82V2041E SHORT HAUL LINE INTER- FACE UNIT FEATURES Single channel T1/E1/J1 short haul line interfaces - PRBS (Pseudo Random Bit Sequence) generation and detection 15 Supports HPS (Hitless Protection Switching) for 1+1 protection with 2 -1 PRBS polynomials for E1 without external relays - QRSS (Quasi Random Sequence Signals) generation and detection Programmable T1/E1/J1 switchability allowing one bill of ma- 20 with 2 -1 QRSS polynomials for T1/J1 terial for any line condition - 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS Single 3.3 V power supply with 5 V tolerance on digital interfaces error counter Meets or exceeds specifications in - Analog loopback, Digital loopback, Remote loopback and Inband - ANSI T1.102, T1.403 and T1.408 loopback - ITU I.431, G.703, G.736, G.775 and G.823 Adaptive receive sensitivity up to -20 dB (Host Mode only) - ETSI 300-166, 300-233 and TBR12/13 Short circuit protection and internal protection diode for line - AT&T Pub 62411 drivers Software programmable or hardware selectable on: LOS (Loss Of Signal) detection with programmable LOS levels - Wave-shaping templates (Host Mode only) - Line terminating impedance (T1:100 , J1:110 , E1:75 /120 ) AIS (Alarm Indication Signal) detection - Adjustment of arbitrary pulse shape Supports serial control interface, Motorola and Intel Multiplexed - JA (Jitter Attenuator) position (receive path or transmit path) interfaces and hardware control mode - Single rail/dual rail system interfaces Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU - B8ZS/HDB3/AMI line encoding/decoding and 82V2051E E1 Short Haul LIU - Active edge of transmit clock (TCLK) and receive clock (RCLK) Package: - Active level of transmit data (TDATA) and receive data (RDATA) Available in 44-pin TQFP packages - Receiver or transmitter power down Green package options available - High impedance setting for line drivers DESCRIPTION The IDT82V2041E can be configured as a single channel T1, E1 or J1 chip, and different types of loopbacks can be set according to the applica- Line Interface Unit. The IDT82V2041E performs clock/data recovery, AMI/ tions. Four different kinds of line terminating impedance, 75 , 100 , 110 B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An and 120 are selectable. The chip also provides driver short-circuit pro- integrated Adaptive Equalizer is available to increase the receive sensitivity tection and internal protection diode. The chip can be controlled by either and enable programming of LOS levels. In transmit path, there is an AMI/ software or hardware. B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenua- The IDT82V2041E can be used in LAN, WAN, Routers, Wireless Base tor, which can be placed in either the receive path or the transmit path. The Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, Jitter Attenuator can also be disabled. The IDT82V2041E supports both CSU/DSU equipment, etc. Single Rail and Dual Rail system interfaces. To facilitate the network main- tenance, a PRBS/QRSS generation/detection circuit is integrated in the 1 December 9, 2005 DSC-6775/1IDT82V2041E SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM LOS/AIS LOS Detector Receiver RCLK Data and Adaptive RTIP B8ZS/ Data Jitter Internal RD/RDP Clock Equalizer HDB3/AMI Slicer Attenuator Termination RRING Recovery CV/RDN Decoder PRBS Detector Analog Remote Digital Loopback IBLC Detector Loopback Loopback TCLK TTIP B8ZS/ Transmitter Jitter Line Waveform TD/TDP HDB3/AMI Internal Attenuator Driver TRING Shaper TDN Decoder Termination PRBS Generator IBLC Generator TAOS Clock Register Software Control Interface Pin Control Generator Files VDDIO VDDD VDDA VDDT Figure-1 Block Diagram Functional Block Diagram 2 December 9, 2005 MCLK INT CS SDO / ACK / RDY SCLK/ALE/AS RD / DS / SCLKE SDI/ WR /R/W AD 7:0 MODE 1:0 TERM RXTXM 1:0 PULS 3:0 PATT 1:0 JA 1:0 MONT LP 1:0 THZ RCLKE RPD RST