DUAL CHANNEL T1/E1/J1 SHORT IDT82V2042E HAUL LINE INTERFACE UNIT FEATURES: Dual channel T1/E1/J1 short haul line interfaces - PRBS (Pseudo Random Bit Sequence) generation and detection 15 Supports HPS (Hitless Protection Switching) for 1+1 protection with 2 -1 PRBS polynomials for E1 without external relays - QRSS (Quasi Random Sequence Signals) generation and detection Programmable T1/E1/J1 switchability allowing one bill of ma- 20 with 2 -1 QRSS polynomials for T1/J1 terial for any line condition - 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS Single 3.3 V power supply with 5 V tolerance on digital interfaces error counter Meets or exceeds specifications in - Analog loopback, Digital loopback, Remote loopback and Inband - ANSI T1.102, T1.403 and T1.408 loopback - ITU I.431, G.703, G.736, G.775 and G.823 Adaptive receive sensitivity up to -20 dB (Host Mode only) - ETSI 300-166, 300-233 and TBR12/13 Non-intrusive monitoring per ITU G.772 specification - AT&T Pub 62411 Short circuit protection and internal protection diode for line Software programmable or hardware selectable on: drivers - Wave-shaping templates LOS (Loss Of Signal) detection with programmable LOS levels - Line terminating impedance (T1:100 , J1:110 , E1: 75 /120 ) (Host Mode only) - Adjustment of arbitrary pulse shape AIS (Alarm Indication Signal) detection - JA (Jitter Attenuator) position (receive path or transmit path) JTAG interface - Single rail/dual rail system interfaces Supports serial control interface, Motorola and Intel Non-Multi- - B8ZS/HDB3/AMI line encoding/decoding plexed interfaces and hardware control mode - Active edge of transmit clock (TCLK) and receive clock (RCLK) Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU - Active level of transmit data (TDATA) and receive data (RDATA) and 82V2052E E1 Short Haul LIU - Receiver or transmitter power down Available in 80-pin TQFP - High impedance setting for line drivers Green package options available DESCRIPTION: The IDT82V2042E can be configured as a dual channel T1, E1 or J1 Line ferent types of loopbacks can be set according to the applications. Four dif- Interface Unit. The IDT82V2042E performs clock/data recovery, AMI/ ferent kinds of line terminating impedance, 75 ,100 , 110 and 120 B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An are selectable on a per channel basis. The chip also provides driver short- integrated Adaptive Equalizer is available to increase the receive sensitivity circuit protection and internal protection diode and supports JTAG bound- and enable programming of LOS levels. In transmit path, there is an AMI/ ary scanning. The chip can be controlled by either software or hardware. B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator, The IDT82V2042E can be used in LAN, WAN, Routers, Wireless Base which can be placed in either the receive path or the transmit path. The Jitter Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, Attenuator can also be disabled. The IDT82V2042E supports both Single CSU/DSU equipment, etc. Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in the chip, and dif- .IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 December 12, 2005 DSC-6774/1IDT82V2042E DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM One of the Two Identical Channels LOSn LOS/AIS Detector RCLKn Data and Receiver Adaptive RTIPn B8ZS/ Data Jitter Internal RDn/RDPn Clock Equalizer HDB3/AMI Slicer Attenuator Termination RRINGn CVn/RDNn Recovery Decoder PRBS Detector Remote Analog Digital IBLC Detector Loopback Loopback Loopback TCLKn TTIPn B8ZS/ Transmitter Jitter Line Waveform TDn/TDPn HDB3/AMI Internal Attenuator Driver Shaper TRINGn TDNn Decoder Termination PRBS Generator IBLC Generator TAOS Clock Register Software Control Interface Pin Control JTAG TAP Generator Files G.772 Monitor VDDIO VDDD VDDA VDDT VDDR Figure-1 Block Diagram FUNCTIONAL BLOCK DIAGRAM 2 December 12, 2005 MCLK INT CS SDO SCLK R/W/WR/SDI RD/DS/SCLKE A 5:0 D 7:0 MODE 1:0 TERMn RXTXM 1:0 PULSn 3:0 PATTn 1:0 JA 1:0 MONTn LPn 1:0 THZ RCLKE RPDn RST TRST TCK TMS TDI TDO